📄 stm8s_uart3.ls
字号:
1788 0271 c45247 and a,21063
1789 0274 2728 jreq L747
1790 ; 622 status = SET;
1792 0276 2021 jp LC007
1793 ; 627 status = RESET;
1794 0278 L147:
1795 ; 630 else if (UART3_FLAG == UART3_FLAG_SBK)
1797 0278 1e02 ldw x,(OFST+1,sp)
1798 027a a30101 cpw x,#257
1799 027d 2609 jrne L157
1800 ; 632 if ((UART3->CR2 & (u8)UART3_FLAG) != (u8)0x00)
1802 027f c65245 ld a,21061
1803 0282 1503 bcp a,(OFST+2,sp)
1804 0284 2717 jreq L567
1805 ; 635 status = SET;
1807 0286 2011 jp LC007
1808 ; 640 status = RESET;
1809 0288 L157:
1810 ; 643 else if ((UART3_FLAG == UART3_FLAG_LHDF) || (UART3_FLAG == UART3_FLAG_LSF))
1812 0288 a30302 cpw x,#770
1813 028b 2705 jreq L367
1815 028d a30301 cpw x,#769
1816 0290 260f jrne L167
1817 0292 L367:
1818 ; 645 if ((UART3->CR6 & (u8)UART3_FLAG) != (u8)0x00)
1820 0292 c65249 ld a,21065
1821 0295 1503 bcp a,(OFST+2,sp)
1822 0297 2704 jreq L567
1823 ; 648 status = SET;
1825 0299 LC007:
1829 0299 a601 ld a,#1
1832 029b 2001 jra L747
1833 029d L567:
1834 ; 653 status = RESET;
1838 029d 4f clr a
1839 029e L747:
1840 ; 671 return status;
1844 029e 5b03 addw sp,#3
1845 02a0 81 ret
1846 02a1 L167:
1847 ; 658 if ((UART3->SR & (u8)UART3_FLAG) != (u8)0x00)
1849 02a1 c65240 ld a,21056
1850 02a4 1503 bcp a,(OFST+2,sp)
1851 02a6 27f5 jreq L567
1852 ; 661 status = SET;
1854 02a8 20ef jp LC007
1855 ; 666 status = RESET;
1890 ; 708 void UART3_ClearFlag(UART3_Flag_TypeDef UART3_FLAG)
1890 ; 709 {
1891 switch .text
1892 02aa _UART3_ClearFlag:
1894 02aa 89 pushw x
1895 00000000 OFST: set 0
1898 ; 710 assert_param(IS_UART3_CLEAR_FLAG_OK(UART3_FLAG));
1900 ; 713 if (UART3_FLAG == UART3_FLAG_RXNE)
1902 02ab a30020 cpw x,#32
1903 02ae 2606 jrne L5101
1904 ; 715 UART3->SR = (u8)~(UART3_SR_RXNE);
1906 02b0 35df5240 mov 21056,#223
1908 02b4 201c jra L7101
1909 02b6 L5101:
1910 ; 718 else if (UART3_FLAG == UART3_FLAG_LBDF)
1912 02b6 1e01 ldw x,(OFST+1,sp)
1913 02b8 a30210 cpw x,#528
1914 02bb 2606 jrne L1201
1915 ; 720 UART3->CR4 &= (u8)(~UART3_CR4_LBDF);
1917 02bd 72195247 bres 21063,#4
1919 02c1 200f jra L7101
1920 02c3 L1201:
1921 ; 723 else if (UART3_FLAG == UART3_FLAG_LHDF)
1923 02c3 a30302 cpw x,#770
1924 02c6 2606 jrne L5201
1925 ; 725 UART3->CR6 &= (u8)(~UART3_CR6_LHDF);
1927 02c8 72135249 bres 21065,#1
1929 02cc 2004 jra L7101
1930 02ce L5201:
1931 ; 730 UART3->CR6 &= (u8)(~UART3_CR6_LSF);
1933 02ce 72115249 bres 21065,#0
1934 02d2 L7101:
1935 ; 733 }
1938 02d2 85 popw x
1939 02d3 81 ret
2021 ; 760 ITStatus UART3_GetITStatus(UART3_IT_TypeDef UART3_IT)
2021 ; 761 {
2022 switch .text
2023 02d4 _UART3_GetITStatus:
2025 02d4 89 pushw x
2026 02d5 89 pushw x
2027 00000002 OFST: set 2
2030 ; 762 ITStatus pendingbitstatus = RESET;
2032 ; 763 u8 itpos = 0;
2034 ; 764 u8 itmask1 = 0;
2036 ; 765 u8 itmask2 = 0;
2038 ; 766 u8 enablestatus = 0;
2040 ; 769 assert_param(IS_UART3_GET_IT_OK(UART3_IT));
2042 ; 772 itpos = (u8)((u8)1 << (u8)((u8)UART3_IT & (u8)0x0F));
2044 02d6 7b04 ld a,(OFST+2,sp)
2045 02d8 a40f and a,#15
2046 02da 5f clrw x
2047 02db 97 ld xl,a
2048 02dc a601 ld a,#1
2049 02de 5d tnzw x
2050 02df 2704 jreq L26
2051 02e1 L46:
2052 02e1 48 sll a
2053 02e2 5a decw x
2054 02e3 26fc jrne L46
2055 02e5 L26:
2056 02e5 6b01 ld (OFST-1,sp),a
2057 ; 774 itmask1 = (u8)((u8)UART3_IT >> (u8)4);
2059 02e7 7b04 ld a,(OFST+2,sp)
2060 02e9 4e swap a
2061 02ea a40f and a,#15
2062 02ec 6b02 ld (OFST+0,sp),a
2063 ; 776 itmask2 = (u8)((u8)1 << itmask1);
2065 02ee 5f clrw x
2066 02ef 97 ld xl,a
2067 02f0 a601 ld a,#1
2068 02f2 5d tnzw x
2069 02f3 2704 jreq L66
2070 02f5 L07:
2071 02f5 48 sll a
2072 02f6 5a decw x
2073 02f7 26fc jrne L07
2074 02f9 L66:
2075 02f9 6b02 ld (OFST+0,sp),a
2076 ; 781 if (UART3_IT == UART3_IT_PE)
2078 02fb 1e03 ldw x,(OFST+1,sp)
2079 02fd a30100 cpw x,#256
2080 0300 260c jrne L3701
2081 ; 784 enablestatus = (u8)((u8)UART3->CR1 & itmask2);
2083 0302 c65244 ld a,21060
2084 0305 1402 and a,(OFST+0,sp)
2085 0307 6b02 ld (OFST+0,sp),a
2086 ; 787 if (((UART3->SR & itpos) != (u8)0x00) && enablestatus)
2088 0309 c65240 ld a,21056
2090 ; 790 pendingbitstatus = SET;
2092 030c 2020 jp LC010
2093 ; 795 pendingbitstatus = RESET;
2094 030e L3701:
2095 ; 799 else if (UART3_IT == UART3_IT_LBDF)
2097 030e a30346 cpw x,#838
2098 0311 260c jrne L3011
2099 ; 802 enablestatus = (u8)((u8)UART3->CR4 & itmask2);
2101 0313 c65247 ld a,21063
2102 0316 1402 and a,(OFST+0,sp)
2103 0318 6b02 ld (OFST+0,sp),a
2104 ; 804 if (((UART3->CR4 & itpos) != (u8)0x00) && enablestatus)
2106 031a c65247 ld a,21063
2108 ; 807 pendingbitstatus = SET;
2110 031d 200f jp LC010
2111 ; 812 pendingbitstatus = RESET;
2112 031f L3011:
2113 ; 815 else if (UART3_IT == UART3_IT_LHDF)
2115 031f a30412 cpw x,#1042
2116 0322 2616 jrne L3111
2117 ; 818 enablestatus = (u8)((u8)UART3->CR6 & itmask2);
2119 0324 c65249 ld a,21065
2120 0327 1402 and a,(OFST+0,sp)
2121 0329 6b02 ld (OFST+0,sp),a
2122 ; 820 if (((UART3->CR6 & itpos) != (u8)0x00) && enablestatus)
2124 032b c65249 ld a,21065
2126 032e LC010:
2127 032e 1501 bcp a,(OFST-1,sp)
2128 0330 271a jreq L3211
2129 0332 7b02 ld a,(OFST+0,sp)
2130 0334 2716 jreq L3211
2131 ; 823 pendingbitstatus = SET;
2133 0336 LC009:
2137 0336 a601 ld a,#1
2139 0338 2013 jra L1011
2140 ; 828 pendingbitstatus = RESET;
2141 033a L3111:
2142 ; 834 enablestatus = (u8)((u8)UART3->CR2 & itmask2);
2144 033a c65245 ld a,21061
2145 033d 1402 and a,(OFST+0,sp)
2146 033f 6b02 ld (OFST+0,sp),a
2147 ; 836 if (((UART3->SR & itpos) != (u8)0x00) && enablestatus)
2149 0341 c65240 ld a,21056
2150 0344 1501 bcp a,(OFST-1,sp)
2151 0346 2704 jreq L3211
2153 0348 7b02 ld a,(OFST+0,sp)
2154 ; 839 pendingbitstatus = SET;
2156 034a 26ea jrne LC009
2157 034c L3211:
2158 ; 844 pendingbitstatus = RESET;
2163 034c 4f clr a
2164 034d L1011:
2165 ; 848 return pendingbitstatus;
2169 034d 5b04 addw sp,#4
2170 034f 81 ret
2215 ; 884 void UART3_ClearITPendingBit(UART3_IT_TypeDef UART3_IT)
2215 ; 885 {
2216 switch .text
2217 0350 _UART3_ClearITPendingBit:
2219 0350 89 pushw x
2220 0351 88 push a
2221 00000001 OFST: set 1
2224 ; 886 u8 dummy = 0;
2226 0352 0f01 clr (OFST+0,sp)
2227 ; 887 assert_param(IS_UART3_CLEAR_IT_OK(UART3_IT));
2229 ; 890 if (UART3_IT == UART3_IT_RXNE)
2231 0354 a30255 cpw x,#597
2232 0357 2606 jrne L1511
2233 ; 892 UART3->SR = (u8)~(UART3_SR_RXNE);
2235 0359 35df5240 mov 21056,#223
2237 035d 2011 jra L3511
2238 035f L1511:
2239 ; 895 else if (UART3_IT == UART3_IT_LBDF)
2241 035f 1e02 ldw x,(OFST+1,sp)
2242 0361 a30346 cpw x,#838
2243 0364 2606 jrne L5511
2244 ; 897 UART3->CR4 &= (u8)~(UART3_CR4_LBDF);
2246 0366 72195247 bres 21063,#4
2248 036a 2004 jra L3511
2249 036c L5511:
2250 ; 902 UART3->CR6 &= (u8)(~UART3_CR6_LHDF);
2252 036c 72135249 bres 21065,#1
2253 0370 L3511:
2254 ; 904 }
2257 0370 5b03 addw sp,#3
2258 0372 81 ret
2271 xref _CLK_GetClockFreq
2272 xdef _UART3_ClearITPendingBit
2273 xdef _UART3_GetITStatus
2274 xdef _UART3_ClearFlag
2275 xdef _UART3_GetFlagStatus
2276 xdef _UART3_SetAddress
2277 xdef _UART3_SendBreak
2278 xdef _UART3_SendData9
2279 xdef _UART3_SendData8
2280 xdef _UART3_ReceiveData9
2281 xdef _UART3_ReceiveData8
2282 xdef _UART3_WakeUpConfig
2283 xdef _UART3_ReceiverWakeUpCmd
2284 xdef _UART3_LINCmd
2285 xdef _UART3_LINConfig
2286 xdef _UART3_LINBreakDetectionConfig
2287 xdef _UART3_ITConfig
2288 xdef _UART3_Cmd
2289 xdef _UART3_Init
2290 xdef _UART3_DeInit
2291 xref.b c_lreg
2292 xref.b c_x
2311 xref c_lursh
2312 xref c_lsub
2313 xref c_smul
2314 xref c_ludv
2315 xref c_rtol
2316 xref c_llsh
2317 xref c_ltor
2318 end
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