📄 stm8s_tim2.ls
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2319 ; 923 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC1P);
2321 026d 72135308 bres 21256,#1
2322 ; 925 }
2325 0271 81 ret
2361 ; 945 void TIM2_OC2PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
2361 ; 946 {
2362 switch .text
2363 0272 _TIM2_OC2PolarityConfig:
2367 ; 948 assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
2369 ; 951 if (TIM2_OCPolarity != TIM2_OCPOLARITY_HIGH)
2371 0272 4d tnz a
2372 0273 2705 jreq L3121
2373 ; 953 TIM2->CCER1 |= TIM2_CCER1_CC2P;
2375 0275 721a5308 bset 21256,#5
2378 0279 81 ret
2379 027a L3121:
2380 ; 957 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC2P);
2382 027a 721b5308 bres 21256,#5
2383 ; 959 }
2386 027e 81 ret
2422 ; 979 void TIM2_OC3PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
2422 ; 980 {
2423 switch .text
2424 027f _TIM2_OC3PolarityConfig:
2428 ; 982 assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
2430 ; 985 if (TIM2_OCPolarity != TIM2_OCPOLARITY_HIGH)
2432 027f 4d tnz a
2433 0280 2705 jreq L5321
2434 ; 987 TIM2->CCER2 |= TIM2_CCER2_CC3P;
2436 0282 72125309 bset 21257,#1
2439 0286 81 ret
2440 0287 L5321:
2441 ; 991 TIM2->CCER2 &= (u8)(~TIM2_CCER2_CC3P);
2443 0287 72135309 bres 21257,#1
2444 ; 993 }
2447 028b 81 ret
2492 ; 1016 void TIM2_CCxCmd(TIM2_Channel_TypeDef TIM2_Channel, FunctionalState NewState)
2492 ; 1017 {
2493 switch .text
2494 028c _TIM2_CCxCmd:
2496 028c 89 pushw x
2497 00000000 OFST: set 0
2500 ; 1019 assert_param(IS_TIM2_CHANNEL_OK(TIM2_Channel));
2502 ; 1020 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2504 ; 1022 if (TIM2_Channel == TIM2_CHANNEL_1)
2506 028d 9e ld a,xh
2507 028e 4d tnz a
2508 028f 2610 jrne L3621
2509 ; 1025 if (NewState != DISABLE)
2511 0291 9f ld a,xl
2512 0292 4d tnz a
2513 0293 2706 jreq L5621
2514 ; 1027 TIM2->CCER1 |= TIM2_CCER1_CC1E;
2516 0295 72105308 bset 21256,#0
2518 0299 2029 jra L1721
2519 029b L5621:
2520 ; 1031 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC1E);
2522 029b 72115308 bres 21256,#0
2523 029f 2023 jra L1721
2524 02a1 L3621:
2525 ; 1035 else if (TIM2_Channel == TIM2_CHANNEL_2)
2527 02a1 7b01 ld a,(OFST+1,sp)
2528 02a3 4a dec a
2529 02a4 2610 jrne L3721
2530 ; 1038 if (NewState != DISABLE)
2532 02a6 7b02 ld a,(OFST+2,sp)
2533 02a8 2706 jreq L5721
2534 ; 1040 TIM2->CCER1 |= TIM2_CCER1_CC2E;
2536 02aa 72185308 bset 21256,#4
2538 02ae 2014 jra L1721
2539 02b0 L5721:
2540 ; 1044 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC2E);
2542 02b0 72195308 bres 21256,#4
2543 02b4 200e jra L1721
2544 02b6 L3721:
2545 ; 1050 if (NewState != DISABLE)
2547 02b6 7b02 ld a,(OFST+2,sp)
2548 02b8 2706 jreq L3031
2549 ; 1052 TIM2->CCER2 |= TIM2_CCER2_CC3E;
2551 02ba 72105309 bset 21257,#0
2553 02be 2004 jra L1721
2554 02c0 L3031:
2555 ; 1056 TIM2->CCER2 &= (u8)(~TIM2_CCER2_CC3E);
2557 02c0 72115309 bres 21257,#0
2558 02c4 L1721:
2559 ; 1059 }
2562 02c4 85 popw x
2563 02c5 81 ret
2608 ; 1090 void TIM2_SelectOCxM(TIM2_Channel_TypeDef TIM2_Channel, TIM2_OCMode_TypeDef TIM2_OCMode)
2608 ; 1091 {
2609 switch .text
2610 02c6 _TIM2_SelectOCxM:
2612 02c6 89 pushw x
2613 00000000 OFST: set 0
2616 ; 1093 assert_param(IS_TIM2_CHANNEL_OK(TIM2_Channel));
2618 ; 1094 assert_param(IS_TIM2_OCM_OK(TIM2_OCMode));
2620 ; 1096 if (TIM2_Channel == TIM2_CHANNEL_1)
2622 02c7 9e ld a,xh
2623 02c8 4d tnz a
2624 02c9 2610 jrne L1331
2625 ; 1099 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC1E);
2627 02cb 72115308 bres 21256,#0
2628 ; 1102 TIM2->CCMR1 = (u8)((TIM2->CCMR1 & (u8)(~TIM2_CCMR_OCM)) | (u8)TIM2_OCMode);
2630 02cf c65305 ld a,21253
2631 02d2 a48f and a,#143
2632 02d4 1a02 or a,(OFST+2,sp)
2633 02d6 c75305 ld 21253,a
2635 02d9 2023 jra L3331
2636 02db L1331:
2637 ; 1104 else if (TIM2_Channel == TIM2_CHANNEL_2)
2639 02db 7b01 ld a,(OFST+1,sp)
2640 02dd 4a dec a
2641 02de 2610 jrne L5331
2642 ; 1107 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC2E);
2644 02e0 72195308 bres 21256,#4
2645 ; 1110 TIM2->CCMR2 = (u8)((TIM2->CCMR2 & (u8)(~TIM2_CCMR_OCM)) | (u8)TIM2_OCMode);
2647 02e4 c65306 ld a,21254
2648 02e7 a48f and a,#143
2649 02e9 1a02 or a,(OFST+2,sp)
2650 02eb c75306 ld 21254,a
2652 02ee 200e jra L3331
2653 02f0 L5331:
2654 ; 1115 TIM2->CCER2 &= (u8)(~TIM2_CCER2_CC3E);
2656 02f0 72115309 bres 21257,#0
2657 ; 1118 TIM2->CCMR3 = (u8)((TIM2->CCMR3 & (u8)(~TIM2_CCMR_OCM)) | (u8)TIM2_OCMode);
2659 02f4 c65307 ld a,21255
2660 02f7 a48f and a,#143
2661 02f9 1a02 or a,(OFST+2,sp)
2662 02fb c75307 ld 21255,a
2663 02fe L3331:
2664 ; 1120 }
2667 02fe 85 popw x
2668 02ff 81 ret
2702 ; 1138 void TIM2_SetCounter(u16 Counter)
2702 ; 1139 {
2703 switch .text
2704 0300 _TIM2_SetCounter:
2708 ; 1141 TIM2->CNTRH = (u8)(Counter >> 8);
2710 0300 9e ld a,xh
2711 0301 c7530a ld 21258,a
2712 ; 1142 TIM2->CNTRL = (u8)(Counter);
2714 0304 9f ld a,xl
2715 0305 c7530b ld 21259,a
2716 ; 1144 }
2719 0308 81 ret
2753 ; 1162 void TIM2_SetAutoreload(u16 Autoreload)
2753 ; 1163 {
2754 switch .text
2755 0309 _TIM2_SetAutoreload:
2759 ; 1166 TIM2->ARRH = (u8)(Autoreload >> 8);
2761 0309 9e ld a,xh
2762 030a c7530d ld 21261,a
2763 ; 1167 TIM2->ARRL = (u8)(Autoreload);
2765 030d 9f ld a,xl
2766 030e c7530e ld 21262,a
2767 ; 1169 }
2770 0311 81 ret
2804 ; 1187 void TIM2_SetCompare1(u16 Compare1)
2804 ; 1188 {
2805 switch .text
2806 0312 _TIM2_SetCompare1:
2810 ; 1190 TIM2->CCR1H = (u8)(Compare1 >> 8);
2812 0312 9e ld a,xh
2813 0313 c7530f ld 21263,a
2814 ; 1191 TIM2->CCR1L = (u8)(Compare1);
2816 0316 9f ld a,xl
2817 0317 c75310 ld 21264,a
2818 ; 1193 }
2821 031a 81 ret
2855 ; 1211 void TIM2_SetCompare2(u16 Compare2)
2855 ; 1212 {
2856 switch .text
2857 031b _TIM2_SetCompare2:
2861 ; 1214 TIM2->CCR2H = (u8)(Compare2 >> 8);
2863 031b 9e ld a,xh
2864 031c c75311 ld 21265,a
2865 ; 1215 TIM2->CCR2L = (u8)(Compare2);
2867 031f 9f ld a,xl
2868 0320 c75312 ld 21266,a
2869 ; 1217 }
2872 0323 81 ret
2906 ; 1235 void TIM2_SetCompare3(u16 Compare3)
2906 ; 1236 {
2907 switch .text
2908 0324 _TIM2_SetCompare3:
2912 ; 1238 TIM2->CCR3H = (u8)(Compare3 >> 8);
2914 0324 9e ld a,xh
2915 0325 c75313 ld 21267,a
2916 ; 1239 TIM2->CCR3L = (u8)(Compare3);
2918 0328 9f ld a,xl
2919 0329 c75314 ld 21268,a
2920 ; 1241 }
2923 032c 81 ret
2959 ; 1263 void TIM2_SetIC1Prescaler(TIM2_ICPSC_TypeDef TIM2_IC1Prescaler)
2959 ; 1264 {
2960 switch .text
2961 032d _TIM2_SetIC1Prescaler:
2963 032d 88 push a
2964 00000000 OFST: set 0
2967 ; 1266 assert_param(IS_TIM2_IC_PRESCALER_OK(TIM2_IC1Prescaler));
2969 ; 1269 TIM2->CCMR1 = (u8)((TIM2->CCMR1 & (u8)(~TIM2_CCMR_ICxPSC)) | (u8)TIM2_IC1Prescaler);
2971 032e c65305 ld a,21253
2972 0331 a4f3 and a,#243
2973 0333 1a01 or a,(OFST+1,sp)
2974 0335 c75305 ld 21253,a
2975 ; 1270 }
2978 0338 84 pop a
2979 0339 81 ret
3015 ; 1291 void TIM2_SetIC2Prescaler(TIM2_ICPSC_TypeDef TIM2_IC2Prescaler)
3015 ; 1292 {
3016 switch .text
3017 033a _TIM2_SetIC2Prescaler:
3019 033a 88 push a
3020 00000000 OFST: set 0
3023 ; 1294 assert_param(IS_TIM2_IC_PRESCALER_OK(TIM2_IC2Prescaler));
3025 ; 1297 TIM2->CCMR2 = (u8)((TIM2->CCMR2 & (u8)(~TIM2_CCMR_ICxPSC)) | (u8)TIM2_IC2Prescaler);
3027 033b c65306 ld a,21254
3028 033e a4f3 and a,#243
3029 0340 1a01 or a,(OFST+1,sp)
3030 0342 c75306 ld 21254,a
3031 ; 1298 }
3034 0345 84 pop a
3035 0346 81 ret
3071 ; 1319 void TIM2_SetIC3Prescaler(TIM2_ICPSC_TypeDef TIM2_IC3Prescaler)
3071 ; 1320 {
3072 switch .text
3073 0347 _TIM2_SetIC3Prescaler:
3075 0347 88 push a
3076 00000000 OFST: set 0
3079 ; 1323 assert_param(IS_TIM2_IC_PRESCALER_OK(TIM2_IC3Prescaler));
3081 ; 1325 TIM2->CCMR3 = (u8)((TIM2->CCMR3 & (u8)(~TIM2_CCMR_ICxPSC)) | (u8)TIM2_IC3Prescaler);
3083 0348 c65307 ld a,21255
3084 034b a4f3 and a,#243
3085 034d 1a01 or a,(OFST+1,sp)
3086 034f c75307 ld 21255,a
3087 ; 1326 }
3090 0352 84 pop a
3091 0353 81 ret
3143 ; 1344 u16 TIM2_GetCapture1(void)
3143 ; 1345 {
3144 switch .text
3145 0354 _TIM2_GetCapture1:
3147 0354 5204 subw sp,#4
3148 00000004 OFST: set 4
3151 ; 1347 u16 tmpccr1 = 0;
3153 ; 1348 u8 tmpccr1l=0, tmpccr1h=0;
3157 ; 1350 tmpccr1h = TIM2->CCR1H;
3159 0356 c6530f ld a,21263
3160 0359 6b02 ld (OFST-2,sp),a
3161 ; 1351 tmpccr1l = TIM2->CCR1L;
3163 035b c65310 ld a,21264
3164 035e 6b01 ld (OFST-3,sp),a
3165 ; 1353 tmpccr1 = (u16)(tmpccr1l);
3167 0360 5f clrw x
3168 0361 97 ld xl,a
3169 0362 1f03 ldw (OFST-1,sp),x
3170 ; 1354 tmpccr1 |= (u16)((u16)tmpccr1h << 8);
3172 0364 7b02 ld a,(OFST-2,sp)
3173 0366 97 ld xl,a
3174 0367 7b04 ld a,(OFST+0,sp)
3175 0369 01 rrwa x,a
3176 036a 1a03 or a,(OFST-1,sp)
3177 036c 01 rrwa x,a
3178 ; 1356 return (u16)tmpccr1;
3182 036d 5b04 addw sp,#4
3183 036f 81 ret
3235 ; 1375 u16 TIM2_GetCapture2(void)
3235 ; 1376 {
3236 switch .text
3237 0370 _TIM2_GetCapture2:
3239 0370 5204 subw sp,#4
3240 00000004 OFST: set 4
3243 ; 1378 u16 tmpccr2 = 0;
3245 ; 1379 u8 tmpccr2l=0, tmpccr2h=0;
3249 ; 1381 tmpccr2h = TIM2->CCR2H;
3251 0372 c65311 ld a,21265
3252 0375 6b02 ld (OFST-2,sp),a
3253 ; 1382 tmpccr2l = TIM2->CCR2L;
3255 0377 c65312 ld a,21266
3256 037a 6b01 ld (OFST-3,sp),a
3257 ; 1384 tmpccr2 = (u16)(tmpccr2l);
3259 037c 5f clrw x
3260 037d 97 ld xl,a
3261 037e 1f03 ldw (OFST-1,sp),x
3262 ; 1385 tmpccr2 |= (u16)((u16)tmpccr2h << 8);
3264 0380 7b02 ld a,(OFST-2,sp)
3265 0382 97 ld xl,a
3266 0383 7b04 ld a,(OFST+0,sp)
3267 0385 01 rrwa x,a
3268 0386 1a03 or a,(OFST-1,sp)
3269 0388 01 rrwa x,a
3270 ; 1387 return (u16)tmpccr2;
3274 0389 5b04 addw sp,#4
3275 038b 81 ret
3327 ; 1406 u16 TIM2_GetCapture3(void)
3327 ; 1407 {
3328 switch .text
3329 038c _TIM2_GetCapture3:
3331 038c 5204 subw sp,#4
3332 00000004 OFST: set 4
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