📄 stm8s_tim2.ls
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1151 015c 2002 jra L564
1152 015e L364:
1153 ; 395 icselection = (u8)TIM2_ICSELECTION_DIRECTTI;
1155 015e a601 ld a,#1
1156 0160 L564:
1157 0160 6b02 ld (OFST+0,sp),a
1158 ; 398 if (TIM2_Channel == TIM2_CHANNEL_1)
1160 0162 7b03 ld a,(OFST+1,sp)
1161 0164 2626 jrne L764
1162 ; 401 TI1_Config(TIM2_ICPolarity, TIM2_ICSelection,
1162 ; 402 TIM2_ICFilter);
1164 0166 7b09 ld a,(OFST+7,sp)
1165 0168 88 push a
1166 0169 7b08 ld a,(OFST+6,sp)
1167 016b 97 ld xl,a
1168 016c 7b05 ld a,(OFST+3,sp)
1169 016e 95 ld xh,a
1170 016f cd0418 call L3_TI1_Config
1172 0172 84 pop a
1173 ; 405 TIM2_SetIC1Prescaler(TIM2_ICPrescaler);
1175 0173 7b08 ld a,(OFST+6,sp)
1176 0175 cd032d call _TIM2_SetIC1Prescaler
1178 ; 408 TI2_Config(icpolarity, icselection, TIM2_ICFilter);
1180 0178 7b09 ld a,(OFST+7,sp)
1181 017a 88 push a
1182 017b 7b03 ld a,(OFST+1,sp)
1183 017d 97 ld xl,a
1184 017e 7b02 ld a,(OFST+0,sp)
1185 0180 95 ld xh,a
1186 0181 cd0448 call L5_TI2_Config
1188 0184 84 pop a
1189 ; 411 TIM2_SetIC2Prescaler(TIM2_ICPrescaler);
1191 0185 7b08 ld a,(OFST+6,sp)
1192 0187 cd033a call _TIM2_SetIC2Prescaler
1195 018a 2024 jra L174
1196 018c L764:
1197 ; 416 TI2_Config(TIM2_ICPolarity, TIM2_ICSelection,
1197 ; 417 TIM2_ICFilter);
1199 018c 7b09 ld a,(OFST+7,sp)
1200 018e 88 push a
1201 018f 7b08 ld a,(OFST+6,sp)
1202 0191 97 ld xl,a
1203 0192 7b05 ld a,(OFST+3,sp)
1204 0194 95 ld xh,a
1205 0195 cd0448 call L5_TI2_Config
1207 0198 84 pop a
1208 ; 420 TIM2_SetIC2Prescaler(TIM2_ICPrescaler);
1210 0199 7b08 ld a,(OFST+6,sp)
1211 019b cd033a call _TIM2_SetIC2Prescaler
1213 ; 423 TI1_Config(icpolarity, icselection, TIM2_ICFilter);
1215 019e 7b09 ld a,(OFST+7,sp)
1216 01a0 88 push a
1217 01a1 7b03 ld a,(OFST+1,sp)
1218 01a3 97 ld xl,a
1219 01a4 7b02 ld a,(OFST+0,sp)
1220 01a6 95 ld xh,a
1221 01a7 cd0418 call L3_TI1_Config
1223 01aa 84 pop a
1224 ; 426 TIM2_SetIC1Prescaler(TIM2_ICPrescaler);
1226 01ab 7b08 ld a,(OFST+6,sp)
1227 01ad cd032d call _TIM2_SetIC1Prescaler
1229 01b0 L174:
1230 ; 428 }
1233 01b0 5b04 addw sp,#4
1234 01b2 81 ret
1289 ; 446 void TIM2_Cmd(FunctionalState NewState)
1289 ; 447 {
1290 switch .text
1291 01b3 _TIM2_Cmd:
1295 ; 449 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1297 ; 452 if (NewState != DISABLE)
1299 01b3 4d tnz a
1300 01b4 2705 jreq L125
1301 ; 454 TIM2->CR1 |= TIM2_CR1_CEN;
1303 01b6 72105300 bset 21248,#0
1306 01ba 81 ret
1307 01bb L125:
1308 ; 458 TIM2->CR1 &= (u8)(~TIM2_CR1_CEN);
1310 01bb 72115300 bres 21248,#0
1311 ; 460 }
1314 01bf 81 ret
1393 ; 485 void TIM2_ITConfig(TIM2_IT_TypeDef TIM2_IT, FunctionalState NewState)
1393 ; 486 {
1394 switch .text
1395 01c0 _TIM2_ITConfig:
1397 01c0 89 pushw x
1398 00000000 OFST: set 0
1401 ; 488 assert_param(IS_TIM2_IT_OK(TIM2_IT));
1403 ; 489 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1405 ; 491 if (NewState != DISABLE)
1407 01c1 9f ld a,xl
1408 01c2 4d tnz a
1409 01c3 2706 jreq L365
1410 ; 494 TIM2->IER |= TIM2_IT;
1412 01c5 9e ld a,xh
1413 01c6 ca5301 or a,21249
1415 01c9 2006 jra L565
1416 01cb L365:
1417 ; 499 TIM2->IER &= (u8)(~TIM2_IT);
1419 01cb 7b01 ld a,(OFST+1,sp)
1420 01cd 43 cpl a
1421 01ce c45301 and a,21249
1422 01d1 L565:
1423 01d1 c75301 ld 21249,a
1424 ; 501 }
1427 01d4 85 popw x
1428 01d5 81 ret
1464 ; 519 void TIM2_UpdateDisableConfig(FunctionalState NewState)
1464 ; 520 {
1465 switch .text
1466 01d6 _TIM2_UpdateDisableConfig:
1470 ; 522 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1472 ; 525 if (NewState != DISABLE)
1474 01d6 4d tnz a
1475 01d7 2705 jreq L506
1476 ; 527 TIM2->CR1 |= TIM2_CR1_UDIS;
1478 01d9 72125300 bset 21248,#1
1481 01dd 81 ret
1482 01de L506:
1483 ; 531 TIM2->CR1 &= (u8)(~TIM2_CR1_UDIS);
1485 01de 72135300 bres 21248,#1
1486 ; 533 }
1489 01e2 81 ret
1547 ; 552 void TIM2_UpdateRequestConfig(TIM2_UpdateSource_TypeDef TIM2_UpdateSource)
1547 ; 553 {
1548 switch .text
1549 01e3 _TIM2_UpdateRequestConfig:
1553 ; 555 assert_param(IS_TIM2_UPDATE_SOURCE_OK(TIM2_UpdateSource));
1555 ; 558 if (TIM2_UpdateSource != TIM2_UPDATESOURCE_GLOBAL)
1557 01e3 4d tnz a
1558 01e4 2705 jreq L736
1559 ; 560 TIM2->CR1 |= TIM2_CR1_URS;
1561 01e6 72145300 bset 21248,#2
1564 01ea 81 ret
1565 01eb L736:
1566 ; 564 TIM2->CR1 &= (u8)(~TIM2_CR1_URS);
1568 01eb 72155300 bres 21248,#2
1569 ; 566 }
1572 01ef 81 ret
1629 ; 586 void TIM2_SelectOnePulseMode(TIM2_OPMode_TypeDef TIM2_OPMode)
1629 ; 587 {
1630 switch .text
1631 01f0 _TIM2_SelectOnePulseMode:
1635 ; 589 assert_param(IS_TIM2_OPM_MODE_OK(TIM2_OPMode));
1637 ; 592 if (TIM2_OPMode != TIM2_OPMODE_REPETITIVE)
1639 01f0 4d tnz a
1640 01f1 2705 jreq L176
1641 ; 594 TIM2->CR1 |= TIM2_CR1_OPM;
1643 01f3 72165300 bset 21248,#3
1646 01f7 81 ret
1647 01f8 L176:
1648 ; 598 TIM2->CR1 &= (u8)(~TIM2_CR1_OPM);
1650 01f8 72175300 bres 21248,#3
1651 ; 601 }
1654 01fc 81 ret
1722 ; 641 void TIM2_PrescalerConfig(TIM2_Prescaler_TypeDef Prescaler,
1722 ; 642 TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode)
1722 ; 643 {
1723 switch .text
1724 01fd _TIM2_PrescalerConfig:
1728 ; 645 assert_param(IS_TIM2_PRESCALER_RELOAD_OK(TIM2_PSCReloadMode));
1730 ; 646 assert_param(IS_TIM2_PRESCALER_OK(Prescaler));
1732 ; 649 TIM2->PSCR = Prescaler;
1734 01fd 9e ld a,xh
1735 01fe c7530c ld 21260,a
1736 ; 652 TIM2->EGR = TIM2_PSCReloadMode;
1738 0201 9f ld a,xl
1739 0202 c75304 ld 21252,a
1740 ; 653 }
1743 0205 81 ret
1801 ; 673 void TIM2_ForcedOC1Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
1801 ; 674 {
1802 switch .text
1803 0206 _TIM2_ForcedOC1Config:
1805 0206 88 push a
1806 00000000 OFST: set 0
1809 ; 676 assert_param(IS_TIM2_FORCED_ACTION_OK(TIM2_ForcedAction));
1811 ; 679 TIM2->CCMR1 = (u8)((TIM2->CCMR1 & (u8)(~TIM2_CCMR_OCM)) | (u8)TIM2_ForcedAction);
1813 0207 c65305 ld a,21253
1814 020a a48f and a,#143
1815 020c 1a01 or a,(OFST+1,sp)
1816 020e c75305 ld 21253,a
1817 ; 680 }
1820 0211 84 pop a
1821 0212 81 ret
1857 ; 700 void TIM2_ForcedOC2Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
1857 ; 701 {
1858 switch .text
1859 0213 _TIM2_ForcedOC2Config:
1861 0213 88 push a
1862 00000000 OFST: set 0
1865 ; 703 assert_param(IS_TIM2_FORCED_ACTION_OK(TIM2_ForcedAction));
1867 ; 706 TIM2->CCMR2 = (u8)((TIM2->CCMR2 & (u8)(~TIM2_CCMR_OCM)) | (u8)TIM2_ForcedAction);
1869 0214 c65306 ld a,21254
1870 0217 a48f and a,#143
1871 0219 1a01 or a,(OFST+1,sp)
1872 021b c75306 ld 21254,a
1873 ; 707 }
1876 021e 84 pop a
1877 021f 81 ret
1913 ; 727 void TIM2_ForcedOC3Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
1913 ; 728 {
1914 switch .text
1915 0220 _TIM2_ForcedOC3Config:
1917 0220 88 push a
1918 00000000 OFST: set 0
1921 ; 730 assert_param(IS_TIM2_FORCED_ACTION_OK(TIM2_ForcedAction));
1923 ; 733 TIM2->CCMR3 = (u8)((TIM2->CCMR3 & (u8)(~TIM2_CCMR_OCM)) | (u8)TIM2_ForcedAction);
1925 0221 c65307 ld a,21255
1926 0224 a48f and a,#143
1927 0226 1a01 or a,(OFST+1,sp)
1928 0228 c75307 ld 21255,a
1929 ; 734 }
1932 022b 84 pop a
1933 022c 81 ret
1969 ; 752 void TIM2_ARRPreloadConfig(FunctionalState NewState)
1969 ; 753 {
1970 switch .text
1971 022d _TIM2_ARRPreloadConfig:
1975 ; 755 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1977 ; 758 if (NewState != DISABLE)
1979 022d 4d tnz a
1980 022e 2705 jreq L7201
1981 ; 760 TIM2->CR1 |= TIM2_CR1_ARPE;
1983 0230 721e5300 bset 21248,#7
1986 0234 81 ret
1987 0235 L7201:
1988 ; 764 TIM2->CR1 &= (u8)(~TIM2_CR1_ARPE);
1990 0235 721f5300 bres 21248,#7
1991 ; 766 }
1994 0239 81 ret
2030 ; 784 void TIM2_OC1PreloadConfig(FunctionalState NewState)
2030 ; 785 {
2031 switch .text
2032 023a _TIM2_OC1PreloadConfig:
2036 ; 787 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2038 ; 790 if (NewState != DISABLE)
2040 023a 4d tnz a
2041 023b 2705 jreq L1501
2042 ; 792 TIM2->CCMR1 |= TIM2_CCMR_OCxPE;
2044 023d 72165305 bset 21253,#3
2047 0241 81 ret
2048 0242 L1501:
2049 ; 796 TIM2->CCMR1 &= (u8)(~TIM2_CCMR_OCxPE);
2051 0242 72175305 bres 21253,#3
2052 ; 798 }
2055 0246 81 ret
2091 ; 816 void TIM2_OC2PreloadConfig(FunctionalState NewState)
2091 ; 817 {
2092 switch .text
2093 0247 _TIM2_OC2PreloadConfig:
2097 ; 819 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2099 ; 822 if (NewState != DISABLE)
2101 0247 4d tnz a
2102 0248 2705 jreq L3701
2103 ; 824 TIM2->CCMR2 |= TIM2_CCMR_OCxPE;
2105 024a 72165306 bset 21254,#3
2108 024e 81 ret
2109 024f L3701:
2110 ; 828 TIM2->CCMR2 &= (u8)(~TIM2_CCMR_OCxPE);
2112 024f 72175306 bres 21254,#3
2113 ; 830 }
2116 0253 81 ret
2152 ; 848 void TIM2_OC3PreloadConfig(FunctionalState NewState)
2152 ; 849 {
2153 switch .text
2154 0254 _TIM2_OC3PreloadConfig:
2158 ; 851 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2160 ; 854 if (NewState != DISABLE)
2162 0254 4d tnz a
2163 0255 2705 jreq L5111
2164 ; 856 TIM2->CCMR3 |= TIM2_CCMR_OCxPE;
2166 0257 72165307 bset 21255,#3
2169 025b 81 ret
2170 025c L5111:
2171 ; 860 TIM2->CCMR3 &= (u8)(~TIM2_CCMR_OCxPE);
2173 025c 72175307 bres 21255,#3
2174 ; 862 }
2177 0260 81 ret
2250 ; 884 void TIM2_GenerateEvent(TIM2_EventSource_TypeDef TIM2_EventSource)
2250 ; 885 {
2251 switch .text
2252 0261 _TIM2_GenerateEvent:
2256 ; 887 assert_param(IS_TIM2_EVENT_SOURCE_OK(TIM2_EventSource));
2258 ; 890 TIM2->EGR = TIM2_EventSource;
2260 0261 c75304 ld 21252,a
2261 ; 891 }
2264 0264 81 ret
2300 ; 911 void TIM2_OC1PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
2300 ; 912 {
2301 switch .text
2302 0265 _TIM2_OC1PolarityConfig:
2306 ; 914 assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
2308 ; 917 if (TIM2_OCPolarity != TIM2_OCPOLARITY_HIGH)
2310 0265 4d tnz a
2311 0266 2705 jreq L1711
2312 ; 919 TIM2->CCER1 |= TIM2_CCER1_CC1P;
2314 0268 72125308 bset 21256,#1
2317 026c 81 ret
2318 026d L1711:
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