📄 stm8s_uart2.ls
字号:
2004 02ca 81 ret
2038 ; 754 void UART2_SetGuardTime(u8 UART2_GuardTime)
2038 ; 755 {
2039 switch .text
2040 02cb _UART2_SetGuardTime:
2044 ; 757 UART2->GTR = UART2_GuardTime;
2046 02cb c7524a ld 21066,a
2047 ; 758 }
2050 02ce 81 ret
2084 ; 792 void UART2_SetPrescaler(u8 UART2_Prescaler)
2084 ; 793 {
2085 switch .text
2086 02cf _UART2_SetPrescaler:
2090 ; 795 UART2->PSCR = UART2_Prescaler;
2092 02cf c7524b ld 21067,a
2093 ; 796 }
2096 02d2 81 ret
2253 ; 817 FlagStatus UART2_GetFlagStatus(UART2_Flag_TypeDef UART2_FLAG)
2253 ; 818 {
2254 switch .text
2255 02d3 _UART2_GetFlagStatus:
2257 02d3 89 pushw x
2258 02d4 88 push a
2259 00000001 OFST: set 1
2262 ; 819 FlagStatus status = RESET;
2264 02d5 0f01 clr (OFST+0,sp)
2265 ; 822 assert_param(IS_UART2_FLAG_OK(UART2_FLAG));
2267 ; 825 if (UART2_FLAG == UART2_FLAG_LBDF)
2269 02d7 a30210 cpw x,#528
2270 02da 2608 jrne L5511
2271 ; 827 if ((UART2->CR4 & (u8)UART2_FLAG) != (u8)0x00)
2273 02dc 9f ld a,xl
2274 02dd c45247 and a,21063
2275 02e0 2728 jreq L3611
2276 ; 830 status = SET;
2278 02e2 2021 jp LC007
2279 ; 835 status = RESET;
2280 02e4 L5511:
2281 ; 838 else if (UART2_FLAG == UART2_FLAG_SBK)
2283 02e4 1e02 ldw x,(OFST+1,sp)
2284 02e6 a30101 cpw x,#257
2285 02e9 2609 jrne L5611
2286 ; 840 if ((UART2->CR2 & (u8)UART2_FLAG) != (u8)0x00)
2288 02eb c65245 ld a,21061
2289 02ee 1503 bcp a,(OFST+2,sp)
2290 02f0 2717 jreq L1021
2291 ; 843 status = SET;
2293 02f2 2011 jp LC007
2294 ; 848 status = RESET;
2295 02f4 L5611:
2296 ; 851 else if ((UART2_FLAG == UART2_FLAG_LHDF) || (UART2_FLAG == UART2_FLAG_LSF))
2298 02f4 a30302 cpw x,#770
2299 02f7 2705 jreq L7711
2301 02f9 a30301 cpw x,#769
2302 02fc 260f jrne L5711
2303 02fe L7711:
2304 ; 853 if ((UART2->CR6 & (u8)UART2_FLAG) != (u8)0x00)
2306 02fe c65249 ld a,21065
2307 0301 1503 bcp a,(OFST+2,sp)
2308 0303 2704 jreq L1021
2309 ; 856 status = SET;
2311 0305 LC007:
2315 0305 a601 ld a,#1
2318 0307 2001 jra L3611
2319 0309 L1021:
2320 ; 861 status = RESET;
2324 0309 4f clr a
2325 030a L3611:
2326 ; 879 return status;
2330 030a 5b03 addw sp,#3
2331 030c 81 ret
2332 030d L5711:
2333 ; 866 if ((UART2->SR & (u8)UART2_FLAG) != (u8)0x00)
2335 030d c65240 ld a,21056
2336 0310 1503 bcp a,(OFST+2,sp)
2337 0312 27f5 jreq L1021
2338 ; 869 status = SET;
2340 0314 20ef jp LC007
2341 ; 874 status = RESET;
2376 ; 916 void UART2_ClearFlag(UART2_Flag_TypeDef UART2_FLAG)
2376 ; 917 {
2377 switch .text
2378 0316 _UART2_ClearFlag:
2380 0316 89 pushw x
2381 00000000 OFST: set 0
2384 ; 918 assert_param(IS_UART2_CLEAR_FLAG_OK(UART2_FLAG));
2386 ; 921 if (UART2_FLAG == UART2_FLAG_RXNE)
2388 0317 a30020 cpw x,#32
2389 031a 2606 jrne L1321
2390 ; 923 UART2->SR = (u8)~(UART2_SR_RXNE);
2392 031c 35df5240 mov 21056,#223
2394 0320 201c jra L3321
2395 0322 L1321:
2396 ; 926 else if (UART2_FLAG == UART2_FLAG_LBDF)
2398 0322 1e01 ldw x,(OFST+1,sp)
2399 0324 a30210 cpw x,#528
2400 0327 2606 jrne L5321
2401 ; 928 UART2->CR4 &= (u8)(~UART2_CR4_LBDF);
2403 0329 72195247 bres 21063,#4
2405 032d 200f jra L3321
2406 032f L5321:
2407 ; 931 else if (UART2_FLAG == UART2_FLAG_LHDF)
2409 032f a30302 cpw x,#770
2410 0332 2606 jrne L1421
2411 ; 933 UART2->CR6 &= (u8)(~UART2_CR6_LHDF);
2413 0334 72135249 bres 21065,#1
2415 0338 2004 jra L3321
2416 033a L1421:
2417 ; 938 UART2->CR6 &= (u8)(~UART2_CR6_LSF);
2419 033a 72115249 bres 21065,#0
2420 033e L3321:
2421 ; 941 }
2424 033e 85 popw x
2425 033f 81 ret
2507 ; 968 ITStatus UART2_GetITStatus(UART2_IT_TypeDef UART2_IT)
2507 ; 969 {
2508 switch .text
2509 0340 _UART2_GetITStatus:
2511 0340 89 pushw x
2512 0341 89 pushw x
2513 00000002 OFST: set 2
2516 ; 970 ITStatus pendingbitstatus = RESET;
2518 ; 971 u8 itpos = 0;
2520 ; 972 u8 itmask1 = 0;
2522 ; 973 u8 itmask2 = 0;
2524 ; 974 u8 enablestatus = 0;
2526 ; 977 assert_param(IS_UART2_GET_IT_OK(UART2_IT));
2528 ; 980 itpos = (u8)((u8)1 << (u8)((u8)UART2_IT & (u8)0x0F));
2530 0342 7b04 ld a,(OFST+2,sp)
2531 0344 a40f and a,#15
2532 0346 5f clrw x
2533 0347 97 ld xl,a
2534 0348 a601 ld a,#1
2535 034a 5d tnzw x
2536 034b 2704 jreq L67
2537 034d L001:
2538 034d 48 sll a
2539 034e 5a decw x
2540 034f 26fc jrne L001
2541 0351 L67:
2542 0351 6b01 ld (OFST-1,sp),a
2543 ; 982 itmask1 = (u8)((u8)UART2_IT >> (u8)4);
2545 0353 7b04 ld a,(OFST+2,sp)
2546 0355 4e swap a
2547 0356 a40f and a,#15
2548 0358 6b02 ld (OFST+0,sp),a
2549 ; 984 itmask2 = (u8)((u8)1 << itmask1);
2551 035a 5f clrw x
2552 035b 97 ld xl,a
2553 035c a601 ld a,#1
2554 035e 5d tnzw x
2555 035f 2704 jreq L201
2556 0361 L401:
2557 0361 48 sll a
2558 0362 5a decw x
2559 0363 26fc jrne L401
2560 0365 L201:
2561 0365 6b02 ld (OFST+0,sp),a
2562 ; 989 if (UART2_IT == UART2_IT_PE)
2564 0367 1e03 ldw x,(OFST+1,sp)
2565 0369 a30100 cpw x,#256
2566 036c 260c jrne L7031
2567 ; 992 enablestatus = (u8)((u8)UART2->CR1 & itmask2);
2569 036e c65244 ld a,21060
2570 0371 1402 and a,(OFST+0,sp)
2571 0373 6b02 ld (OFST+0,sp),a
2572 ; 995 if (((UART2->SR & itpos) != (u8)0x00) && enablestatus)
2574 0375 c65240 ld a,21056
2576 ; 998 pendingbitstatus = SET;
2578 0378 2020 jp LC010
2579 ; 1003 pendingbitstatus = RESET;
2580 037a L7031:
2581 ; 1007 else if (UART2_IT == UART2_IT_LBDF)
2583 037a a30346 cpw x,#838
2584 037d 260c jrne L7131
2585 ; 1010 enablestatus = (u8)((u8)UART2->CR4 & itmask2);
2587 037f c65247 ld a,21063
2588 0382 1402 and a,(OFST+0,sp)
2589 0384 6b02 ld (OFST+0,sp),a
2590 ; 1012 if (((UART2->CR4 & itpos) != (u8)0x00) && enablestatus)
2592 0386 c65247 ld a,21063
2594 ; 1015 pendingbitstatus = SET;
2596 0389 200f jp LC010
2597 ; 1020 pendingbitstatus = RESET;
2598 038b L7131:
2599 ; 1023 else if (UART2_IT == UART2_IT_LHDF)
2601 038b a30412 cpw x,#1042
2602 038e 2616 jrne L7231
2603 ; 1026 enablestatus = (u8)((u8)UART2->CR6 & itmask2);
2605 0390 c65249 ld a,21065
2606 0393 1402 and a,(OFST+0,sp)
2607 0395 6b02 ld (OFST+0,sp),a
2608 ; 1028 if (((UART2->CR6 & itpos) != (u8)0x00) && enablestatus)
2610 0397 c65249 ld a,21065
2612 039a LC010:
2613 039a 1501 bcp a,(OFST-1,sp)
2614 039c 271a jreq L7331
2615 039e 7b02 ld a,(OFST+0,sp)
2616 03a0 2716 jreq L7331
2617 ; 1031 pendingbitstatus = SET;
2619 03a2 LC009:
2623 03a2 a601 ld a,#1
2625 03a4 2013 jra L5131
2626 ; 1036 pendingbitstatus = RESET;
2627 03a6 L7231:
2628 ; 1042 enablestatus = (u8)((u8)UART2->CR2 & itmask2);
2630 03a6 c65245 ld a,21061
2631 03a9 1402 and a,(OFST+0,sp)
2632 03ab 6b02 ld (OFST+0,sp),a
2633 ; 1044 if (((UART2->SR & itpos) != (u8)0x00) && enablestatus)
2635 03ad c65240 ld a,21056
2636 03b0 1501 bcp a,(OFST-1,sp)
2637 03b2 2704 jreq L7331
2639 03b4 7b02 ld a,(OFST+0,sp)
2640 ; 1047 pendingbitstatus = SET;
2642 03b6 26ea jrne LC009
2643 03b8 L7331:
2644 ; 1052 pendingbitstatus = RESET;
2649 03b8 4f clr a
2650 03b9 L5131:
2651 ; 1056 return pendingbitstatus;
2655 03b9 5b04 addw sp,#4
2656 03bb 81 ret
2701 ; 1092 void UART2_ClearITPendingBit(UART2_IT_TypeDef UART2_IT)
2701 ; 1093 {
2702 switch .text
2703 03bc _UART2_ClearITPendingBit:
2705 03bc 89 pushw x
2706 03bd 88 push a
2707 00000001 OFST: set 1
2710 ; 1094 u8 dummy = 0;
2712 03be 0f01 clr (OFST+0,sp)
2713 ; 1095 assert_param(IS_UART2_CLEAR_IT_OK(UART2_IT));
2715 ; 1098 if (UART2_IT == UART2_IT_RXNE)
2717 03c0 a30255 cpw x,#597
2718 03c3 2606 jrne L5631
2719 ; 1100 UART2->SR = (u8)~(UART2_SR_RXNE);
2721 03c5 35df5240 mov 21056,#223
2723 03c9 2011 jra L7631
2724 03cb L5631:
2725 ; 1103 else if (UART2_IT == UART2_IT_LBDF)
2727 03cb 1e02 ldw x,(OFST+1,sp)
2728 03cd a30346 cpw x,#838
2729 03d0 2606 jrne L1731
2730 ; 1105 UART2->CR4 &= (u8)~(UART2_CR4_LBDF);
2732 03d2 72195247 bres 21063,#4
2734 03d6 2004 jra L7631
2735 03d8 L1731:
2736 ; 1110 UART2->CR6 &= (u8)(~UART2_CR6_LHDF);
2738 03d8 72135249 bres 21065,#1
2739 03dc L7631:
2740 ; 1112 }
2743 03dc 5b03 addw sp,#3
2744 03de 81 ret
2757 xref _CLK_GetClockFreq
2758 xdef _UART2_ClearITPendingBit
2759 xdef _UART2_GetITStatus
2760 xdef _UART2_ClearFlag
2761 xdef _UART2_GetFlagStatus
2762 xdef _UART2_SetPrescaler
2763 xdef _UART2_SetGuardTime
2764 xdef _UART2_SetAddress
2765 xdef _UART2_SendBreak
2766 xdef _UART2_SendData9
2767 xdef _UART2_SendData8
2768 xdef _UART2_ReceiveData9
2769 xdef _UART2_ReceiveData8
2770 xdef _UART2_ReceiverWakeUpCmd
2771 xdef _UART2_WakeUpConfig
2772 xdef _UART2_SmartCardNACKCmd
2773 xdef _UART2_SmartCardCmd
2774 xdef _UART2_LINCmd
2775 xdef _UART2_LINConfig
2776 xdef _UART2_LINBreakDetectionConfig
2777 xdef _UART2_IrDACmd
2778 xdef _UART2_IrDAConfig
2779 xdef _UART2_ITConfig
2780 xdef _UART2_Cmd
2781 xdef _UART2_Init
2782 xdef _UART2_DeInit
2783 xref.b c_lreg
2784 xref.b c_x
2803 xref c_lursh
2804 xref c_lsub
2805 xref c_smul
2806 xref c_ludv
2807 xref c_rtol
2808 xref c_llsh
2809 xref c_ltor
2810 end
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