📄 stm8s_uart2.ls
字号:
1 ; C Compiler for STM8 (COSMIC Software)
2 ; Generator V4.2.8 - 03 Dec 2008
3 ; Optimizer V4.2.8 - 03 Dec 2008
44 ; 65 void UART2_DeInit(void)
44 ; 66 {
46 switch .text
47 0000 _UART2_DeInit:
49 0000 88 push a
50 00000001 OFST: set 1
53 ; 67 u8 dummy = 0;
55 0001 0f01 clr (OFST+0,sp)
56 ; 70 dummy = UART2->SR;
58 0003 c65240 ld a,21056
59 ; 71 dummy = UART2->DR;
61 0006 c65241 ld a,21057
62 ; 73 UART2->BRR2 = UART2_BRR2_RESET_VALUE; /*< Set UART2_BRR2 to reset value 0x00 */
64 0009 725f5243 clr 21059
65 ; 74 UART2->BRR1 = UART2_BRR1_RESET_VALUE; /*< Set UART2_BRR1 to reset value 0x00 */
67 000d 725f5242 clr 21058
68 ; 76 UART2->CR1 = UART2_CR1_RESET_VALUE; /*< Set UART2_CR1 to reset value 0x00 */
70 0011 725f5244 clr 21060
71 ; 77 UART2->CR2 = UART2_CR2_RESET_VALUE; /*< Set UART2_CR2 to reset value 0x00 */
73 0015 725f5245 clr 21061
74 ; 78 UART2->CR3 = UART2_CR3_RESET_VALUE; /*< Set UART2_CR3 to reset value 0x00 */
76 0019 725f5246 clr 21062
77 ; 79 UART2->CR4 = UART2_CR4_RESET_VALUE; /*< Set UART2_CR4 to reset value 0x00 */
79 001d 725f5247 clr 21063
80 ; 80 UART2->CR5 = UART2_CR5_RESET_VALUE; /*< Set UART2_CR5 to reset value 0x00 */
82 0021 725f5248 clr 21064
83 ; 81 UART2->CR6 = UART2_CR6_RESET_VALUE; /*< Set UART2_CR6 to reset value 0x00 */
85 0025 725f5249 clr 21065
86 ; 83 }
89 0029 84 pop a
90 002a 81 ret
411 .const: section .text
412 0000 L41:
413 0000 00000064 dc.l 100
414 ; 103 void UART2_Init(u32 BaudRate, UART2_WordLength_TypeDef WordLength, UART2_StopBits_TypeDef StopBits, UART2_Parity_TypeDef Parity, UART2_SyncMode_TypeDef SyncMode, UART2_Mode_TypeDef Mode)
414 ; 104 {
415 switch .text
416 002b _UART2_Init:
418 002b 520e subw sp,#14
419 0000000e OFST: set 14
422 ; 105 u8 BRR2_1, BRR2_2 = 0;
424 ; 106 u32 BaudRate_Mantissa, BaudRate_Mantissa100 = 0;
426 002d 96 ldw x,sp
427 002e 1c0007 addw x,#OFST-7
428 0031 cd0000 call c_ltor
430 ; 109 assert_param(IS_UART2_BAUDRATE_OK(BaudRate));
432 ; 111 assert_param(IS_UART2_WORDLENGTH_OK(WordLength));
434 ; 113 assert_param(IS_UART2_STOPBITS_OK(StopBits));
436 ; 115 assert_param(IS_UART2_PARITY_OK(Parity));
438 ; 118 assert_param(IS_UART2_MODE_OK((u8)Mode));
440 ; 122 assert_param(IS_UART2_SYNCMODE_OK((u8)SyncMode));
442 ; 124 UART2->CR1 &= (u8)(~UART2_CR1_M); /**< Clear the word length bit */
444 0034 72195244 bres 21060,#4
445 ; 125 UART2->CR1 |= (u8)WordLength; /**< Set the word length bit according to UART2_WordLength value */
447 0038 c65244 ld a,21060
448 003b 1a15 or a,(OFST+7,sp)
449 003d c75244 ld 21060,a
450 ; 127 UART2->CR3 &= (u8)(~UART2_CR3_STOP); /**< Clear the STOP bits */
452 0040 c65246 ld a,21062
453 0043 a4cf and a,#207
454 0045 c75246 ld 21062,a
455 ; 128 UART2->CR3 |= (u8)StopBits; /**< Set the STOP bits number according to UART2_StopBits value */
457 0048 c65246 ld a,21062
458 004b 1a16 or a,(OFST+8,sp)
459 004d c75246 ld 21062,a
460 ; 130 UART2->CR1 &= (u8)(~(UART2_CR1_PCEN | UART2_CR1_PS )); /**< Clear the Parity Control bit */
462 0050 c65244 ld a,21060
463 0053 a4f9 and a,#249
464 0055 c75244 ld 21060,a
465 ; 131 UART2->CR1 |= (u8)Parity; /**< Set the Parity Control bit to UART2_Parity value */
467 0058 c65244 ld a,21060
468 005b 1a17 or a,(OFST+9,sp)
469 005d c75244 ld 21060,a
470 ; 133 UART2->BRR1 &= (u8)(~UART2_BRR1_DIVM); /**< Clear the LSB mantissa of UARTDIV */
472 0060 725f5242 clr 21058
473 ; 134 UART2->BRR2 &= (u8)(~UART2_BRR2_DIVM); /**< Clear the MSB mantissa of UARTDIV */
475 0064 c65243 ld a,21059
476 0067 a40f and a,#15
477 0069 c75243 ld 21059,a
478 ; 135 UART2->BRR2 &= (u8)(~UART2_BRR2_DIVF); /**< Clear the Fraction bits of UARTDIV */
480 006c c65243 ld a,21059
481 006f a4f0 and a,#240
482 0071 c75243 ld 21059,a
483 ; 138 BaudRate_Mantissa = ((u32)CLK_GetClockFreq() / (BaudRate << 4));
485 0074 96 ldw x,sp
486 0075 1c0011 addw x,#OFST+3
487 0078 cd0000 call c_ltor
489 007b a604 ld a,#4
490 007d cd0000 call c_llsh
492 0080 96 ldw x,sp
493 0081 5c incw x
494 0082 cd0000 call c_rtol
496 0085 cd0000 call _CLK_GetClockFreq
498 0088 96 ldw x,sp
499 0089 5c incw x
500 008a cd0000 call c_ludv
502 008d 96 ldw x,sp
503 008e 1c000b addw x,#OFST-3
504 0091 cd0000 call c_rtol
506 ; 139 BaudRate_Mantissa100 = (((u32)CLK_GetClockFreq() * 100) / (BaudRate << 4));
508 0094 96 ldw x,sp
509 0095 1c0011 addw x,#OFST+3
510 0098 cd0000 call c_ltor
512 009b a604 ld a,#4
513 009d cd0000 call c_llsh
515 00a0 96 ldw x,sp
516 00a1 5c incw x
517 00a2 cd0000 call c_rtol
519 00a5 cd0000 call _CLK_GetClockFreq
521 00a8 a664 ld a,#100
522 00aa cd0000 call c_smul
524 00ad 96 ldw x,sp
525 00ae 5c incw x
526 00af cd0000 call c_ludv
528 00b2 96 ldw x,sp
529 00b3 1c0007 addw x,#OFST-7
530 00b6 cd0000 call c_rtol
532 ; 141 BRR2_1 = (u8)((u8)(((BaudRate_Mantissa100 - (BaudRate_Mantissa * 100))
532 ; 142 << 4) / 100) & (u8)0x0F); /**< Set the fraction of UARTDIV */
534 00b9 96 ldw x,sp
535 00ba 1c000b addw x,#OFST-3
536 00bd cd0000 call c_ltor
538 00c0 a664 ld a,#100
539 00c2 cd0000 call c_smul
541 00c5 96 ldw x,sp
542 00c6 5c incw x
543 00c7 cd0000 call c_rtol
545 00ca 96 ldw x,sp
546 00cb 1c0007 addw x,#OFST-7
547 00ce cd0000 call c_ltor
549 00d1 96 ldw x,sp
550 00d2 5c incw x
551 00d3 cd0000 call c_lsub
553 00d6 a604 ld a,#4
554 00d8 cd0000 call c_llsh
556 00db ae0000 ldw x,#L41
557 00de cd0000 call c_ludv
559 00e1 b603 ld a,c_lreg+3
560 00e3 a40f and a,#15
561 00e5 6b05 ld (OFST-9,sp),a
562 ; 143 BRR2_2 = (u8)((BaudRate_Mantissa >> 4) & (u8)0xF0);
564 00e7 96 ldw x,sp
565 00e8 1c000b addw x,#OFST-3
566 00eb cd0000 call c_ltor
568 00ee a604 ld a,#4
569 00f0 cd0000 call c_lursh
571 00f3 b603 ld a,c_lreg+3
572 00f5 a4f0 and a,#240
573 00f7 b703 ld c_lreg+3,a
574 00f9 3f02 clr c_lreg+2
575 00fb 3f01 clr c_lreg+1
576 00fd 3f00 clr c_lreg
577 00ff 6b06 ld (OFST-8,sp),a
578 ; 145 UART2->BRR2 = (u8)(BRR2_1 | BRR2_2);
580 0101 1a05 or a,(OFST-9,sp)
581 0103 c75243 ld 21059,a
582 ; 146 UART2->BRR1 = (u8)BaudRate_Mantissa; /**< Set the LSB mantissa of UARTDIV */
584 0106 7b0e ld a,(OFST+0,sp)
585 0108 c75242 ld 21058,a
586 ; 148 UART2->CR2 &= (u8)~(UART2_CR2_TEN | UART2_CR2_REN); /**< Disable the Transmitter and Receiver before seting the LBCL, CPOL and CPHA bits */
588 010b c65245 ld a,21061
589 010e a4f3 and a,#243
590 0110 c75245 ld 21061,a
591 ; 149 UART2->CR3 &= (u8)~(UART2_CR3_CPOL | UART2_CR3_CPHA | UART2_CR3_LBCL); /**< Clear the Clock Polarity, lock Phase, Last Bit Clock pulse */
593 0113 c65246 ld a,21062
594 0116 a4f8 and a,#248
595 0118 c75246 ld 21062,a
596 ; 150 UART2->CR3 |= (u8)((u8)SyncMode & (u8)(UART2_CR3_CPOL | UART2_CR3_CPHA | UART2_CR3_LBCL)); /**< Set the Clock Polarity, lock Phase, Last Bit Clock pulse */
598 011b 7b18 ld a,(OFST+10,sp)
599 011d a407 and a,#7
600 011f ca5246 or a,21062
601 0122 c75246 ld 21062,a
602 ; 152 if ((u8)Mode & (u8)UART2_MODE_TX_ENABLE)
604 0125 7b19 ld a,(OFST+11,sp)
605 0127 a504 bcp a,#4
606 0129 2706 jreq L112
607 ; 154 UART2->CR2 |= (u8)UART2_CR2_TEN; /**< Set the Transmitter Enable bit */
609 012b 72165245 bset 21061,#3
611 012f 2004 jra L312
612 0131 L112:
613 ; 158 UART2->CR2 &= (u8)(~UART2_CR2_TEN); /**< Clear the Transmitter Disable bit */
615 0131 72175245 bres 21061,#3
616 0135 L312:
617 ; 160 if ((u8)Mode & (u8)UART2_MODE_RX_ENABLE)
619 0135 a508 bcp a,#8
620 0137 2706 jreq L512
621 ; 162 UART2->CR2 |= (u8)UART2_CR2_REN; /**< Set the Receiver Enable bit */
623 0139 72145245 bset 21061,#2
625 013d 2004 jra L712
626 013f L512:
627 ; 166 UART2->CR2 &= (u8)(~UART2_CR2_REN); /**< Clear the Receiver Disable bit */
629 013f 72155245 bres 21061,#2
630 0143 L712:
631 ; 169 if ((u8)SyncMode&(u8)UART2_SYNCMODE_CLOCK_DISABLE)
633 0143 7b18 ld a,(OFST+10,sp)
634 0145 2a06 jrpl L122
635 ; 171 UART2->CR3 &= (u8)(~UART2_CR3_CKEN); /**< Clear the Clock Enable bit */
637 0147 72175246 bres 21062,#3
639 014b 2008 jra L322
640 014d L122:
641 ; 176 UART2->CR3 |= (u8)((u8)SyncMode & UART2_CR3_CKEN);
643 014d a408 and a,#8
644 014f ca5246 or a,21062
645 0152 c75246 ld 21062,a
646 0155 L322:
647 ; 178 }
650 0155 5b0e addw sp,#14
651 0157 81 ret
706 ; 198 void UART2_Cmd(FunctionalState NewState)
706 ; 199 {
707 switch .text
708 0158 _UART2_Cmd:
712 ; 201 if (NewState != DISABLE)
714 0158 4d tnz a
715 0159 2705 jreq L352
716 ; 203 UART2->CR1 &= (u8)(~UART2_CR1_UARTD); /**< UART2 Enable */
718 015b 721b5244 bres 21060,#5
721 015f 81 ret
722 0160 L352:
723 ; 207 UART2->CR1 |= UART2_CR1_UARTD; /**< UART2 Disable (for low power consumption) */
725 0160 721a5244 bset 21060,#5
726 ; 209 }
729 0164 81 ret
861 ; 236 void UART2_ITConfig(UART2_IT_TypeDef UART2_IT, FunctionalState NewState)
861 ; 237 {
862 switch .text
863 0165 _UART2_ITConfig:
865 0165 89 pushw x
866 0166 89 pushw x
867 00000002 OFST: set 2
870 ; 238 u8 uartreg, itpos = 0x00;
872 ; 239 assert_param(IS_UART2_CONFIG_IT_OK(UART2_IT));
874 ; 240 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
876 ; 243 uartreg = (u8)(UART2_IT >> 0x08);
878 0167 7b03 ld a,(OFST+1,sp)
879 0169 6b01 ld (OFST-1,sp),a
880 ; 246 itpos = (u8)((u8)1 << (u8)((u8)UART2_IT & (u8)0x0F));
882 016b 7b04 ld a,(OFST+2,sp)
883 016d a40f and a,#15
884 016f 5f clrw x
885 0170 97 ld xl,a
886 0171 a601 ld a,#1
887 0173 5d tnzw x
888 0174 2704 jreq L22
889 0176 L42:
890 0176 48 sll a
891 0177 5a decw x
892 0178 26fc jrne L42
893 017a L22:
894 017a 6b02 ld (OFST+0,sp),a
895 ; 248 if (NewState != DISABLE)
897 017c 7b07 ld a,(OFST+5,sp)
898 017e 272a jreq L733
899 ; 251 if (uartreg == 0x01)
901 0180 7b01 ld a,(OFST-1,sp)
902 0182 a101 cp a,#1
903 0184 2607 jrne L143
904 ; 253 UART2->CR1 |= itpos;
906 0186 c65244 ld a,21060
907 0189 1a02 or a,(OFST+0,sp)
909 018b 2029 jp LC003
910 018d L143:
911 ; 255 else if (uartreg == 0x02)
913 018d a102 cp a,#2
914 018f 2607 jrne L543
915 ; 257 UART2->CR2 |= itpos;
917 0191 c65245 ld a,21061
918 0194 1a02 or a,(OFST+0,sp)
920 0196 202d jp LC002
921 0198 L543:
922 ; 259 else if (uartreg == 0x03)
924 0198 a103 cp a,#3
925 019a 2607 jrne L153
926 ; 261 UART2->CR4 |= itpos;
928 019c c65247 ld a,21063
929 019f 1a02 or a,(OFST+0,sp)
931 01a1 2031 jp LC004
932 01a3 L153:
933 ; 265 UART2->CR6 |= itpos;
935 01a3 c65249 ld a,21065
936 01a6 1a02 or a,(OFST+0,sp)
937 01a8 2035 jp LC001
938 01aa L733:
939 ; 271 if (uartreg == 0x01)
941 01aa 7b01 ld a,(OFST-1,sp)
942 01ac a101 cp a,#1
943 01ae 260b jrne L753
944 ; 273 UART2->CR1 &= (u8)(~itpos);
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