📄 stm8s_clk.ls
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1860 0226 84 pop a
1861 0227 81 ret
1885 ; 715 void CLK_ClockSecuritySystemEnable(void)
1885 ; 716 {
1886 switch .text
1887 0228 _CLK_ClockSecuritySystemEnable:
1891 ; 718 CLK->CSSR |= CLK_CSSR_CSSEN;
1893 0228 721050c8 bset 20680,#0
1894 ; 719 }
1897 022c 81 ret
1922 ; 736 CLK_Source_TypeDef CLK_GetSYSCLKSource(void)
1922 ; 737 {
1923 switch .text
1924 022d _CLK_GetSYSCLKSource:
1928 ; 738 return((CLK_Source_TypeDef)CLK->CMSR);
1930 022d c650c3 ld a,20675
1933 0230 81 ret
1996 ; 756 u32 CLK_GetClockFreq(void)
1996 ; 757 {
1997 switch .text
1998 0231 _CLK_GetClockFreq:
2000 0231 5209 subw sp,#9
2001 00000009 OFST: set 9
2004 ; 759 u32 clockfrequency = 0;
2006 0233 96 ldw x,sp
2007 0234 1c0005 addw x,#OFST-4
2008 0237 cd0000 call c_ltor
2010 ; 760 CLK_Source_TypeDef clocksource = CLK_SOURCE_HSI;
2012 ; 761 u8 tmp = 0, presc = 0;
2016 ; 764 clocksource = (CLK_Source_TypeDef)CLK->CMSR;
2018 023a c650c3 ld a,20675
2019 023d 6b09 ld (OFST+0,sp),a
2020 ; 766 if (clocksource == CLK_SOURCE_HSI)
2022 023f a1e1 cp a,#225
2023 0241 2634 jrne L3011
2024 ; 768 tmp = (u8)(CLK->CKDIVR & CLK_CKDIVR_HSIDIV);
2026 0243 c650c6 ld a,20678
2027 0246 a418 and a,#24
2028 ; 769 tmp = (u8)(tmp >> 3);
2030 0248 44 srl a
2031 0249 44 srl a
2032 024a 44 srl a
2033 ; 770 presc = HSIDivFactor[tmp];
2035 024b 5f clrw x
2036 024c 97 ld xl,a
2037 024d d60000 ld a,(_HSIDivFactor,x)
2038 0250 6b09 ld (OFST+0,sp),a
2039 ; 771 clockfrequency = HSI_VALUE / presc;
2041 0252 b703 ld c_lreg+3,a
2042 0254 3f02 clr c_lreg+2
2043 0256 3f01 clr c_lreg+1
2044 0258 3f00 clr c_lreg
2045 025a 96 ldw x,sp
2046 025b 5c incw x
2047 025c cd0000 call c_rtol
2049 025f ae2400 ldw x,#9216
2050 0262 bf02 ldw c_lreg+2,x
2051 0264 ae00f4 ldw x,#244
2052 0267 bf00 ldw c_lreg,x
2053 0269 96 ldw x,sp
2054 026a 5c incw x
2055 026b cd0000 call c_ludv
2057 026e 96 ldw x,sp
2058 026f 1c0005 addw x,#OFST-4
2059 0272 cd0000 call c_rtol
2062 0275 2018 jra L5011
2063 0277 L3011:
2064 ; 773 else if ( clocksource == CLK_SOURCE_LSI)
2066 0277 a1d2 cp a,#210
2067 0279 260a jrne L7011
2068 ; 775 clockfrequency = LSI_VALUE;
2070 027b aef400 ldw x,#62464
2071 027e 1f07 ldw (OFST-2,sp),x
2072 0280 ae0001 ldw x,#1
2074 0283 2008 jp LC004
2075 0285 L7011:
2076 ; 779 clockfrequency = HSE_VALUE;
2078 0285 ae3600 ldw x,#13824
2079 0288 1f07 ldw (OFST-2,sp),x
2080 028a ae016e ldw x,#366
2081 028d LC004:
2082 028d 1f05 ldw (OFST-4,sp),x
2083 028f L5011:
2084 ; 782 return((u32)clockfrequency);
2086 028f 96 ldw x,sp
2087 0290 1c0005 addw x,#OFST-4
2088 0293 cd0000 call c_ltor
2092 0296 5b09 addw sp,#9
2093 0298 81 ret
2192 ; 800 void CLK_AdjustHSICalibrationValue(CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue)
2192 ; 801 {
2193 switch .text
2194 0299 _CLK_AdjustHSICalibrationValue:
2196 0299 88 push a
2197 00000000 OFST: set 0
2200 ; 804 assert_param(IS_CLK_HSITRIMVALUE_OK(CLK_HSICalibrationValue));
2202 ; 807 CLK->HSITRIMR = (u8)((CLK->HSITRIMR & (u8)(~CLK_HSITRIMR_HSITRIM))|((u8)CLK_HSICalibrationValue));
2204 029a c650cc ld a,20684
2205 029d a4f8 and a,#248
2206 029f 1a01 or a,(OFST+1,sp)
2207 02a1 c750cc ld 20684,a
2208 ; 809 }
2211 02a4 84 pop a
2212 02a5 81 ret
2236 ; 828 void CLK_SYSCLKEmergencyClear(void)
2236 ; 829 {
2237 switch .text
2238 02a6 _CLK_SYSCLKEmergencyClear:
2242 ; 830 CLK->SWCR &= (u8)(~CLK_SWCR_SWBSY);
2244 02a6 721150c5 bres 20677,#0
2245 ; 831 }
2248 02aa 81 ret
2401 ; 847 FlagStatus CLK_GetFlagStatus(CLK_Flag_TypeDef CLK_FLAG)
2401 ; 848 {
2402 switch .text
2403 02ab _CLK_GetFlagStatus:
2405 02ab 89 pushw x
2406 02ac 5203 subw sp,#3
2407 00000003 OFST: set 3
2410 ; 850 u16 statusreg = 0;
2412 ; 851 u8 tmpreg = 0;
2414 ; 852 FlagStatus bitstatus = RESET;
2416 ; 855 assert_param(IS_CLK_FLAG_OK(CLK_FLAG));
2418 ; 858 statusreg = (u16)((u16)CLK_FLAG & (u16)0xFF00);
2420 02ae 7b04 ld a,(OFST+1,sp)
2421 02b0 97 ld xl,a
2422 02b1 4f clr a
2423 02b2 02 rlwa x,a
2424 02b3 1f01 ldw (OFST-2,sp),x
2425 ; 861 if (statusreg == 0x0100) /* The flag to check is in ICKRregister */
2427 02b5 a30100 cpw x,#256
2428 02b8 2605 jrne L5521
2429 ; 863 tmpreg = CLK->ICKR;
2431 02ba c650c0 ld a,20672
2433 02bd 2021 jra L7521
2434 02bf L5521:
2435 ; 865 else if (statusreg == 0x0200) /* The flag to check is in ECKRregister */
2437 02bf a30200 cpw x,#512
2438 02c2 2605 jrne L1621
2439 ; 867 tmpreg = CLK->ECKR;
2441 02c4 c650c1 ld a,20673
2443 02c7 2017 jra L7521
2444 02c9 L1621:
2445 ; 869 else if (statusreg == 0x0300) /* The flag to check is in SWIC register */
2447 02c9 a30300 cpw x,#768
2448 02cc 2605 jrne L5621
2449 ; 871 tmpreg = CLK->SWCR;
2451 02ce c650c5 ld a,20677
2453 02d1 200d jra L7521
2454 02d3 L5621:
2455 ; 873 else if (statusreg == 0x0400) /* The flag to check is in CSS register */
2457 02d3 a30400 cpw x,#1024
2458 02d6 2605 jrne L1721
2459 ; 875 tmpreg = CLK->CSSR;
2461 02d8 c650c8 ld a,20680
2463 02db 2003 jra L7521
2464 02dd L1721:
2465 ; 879 tmpreg = CLK->CCOR;
2467 02dd c650c9 ld a,20681
2468 02e0 L7521:
2469 02e0 6b03 ld (OFST+0,sp),a
2470 ; 882 if ((tmpreg & (u8)CLK_FLAG) != (u8)RESET)
2472 02e2 7b05 ld a,(OFST+2,sp)
2473 02e4 1503 bcp a,(OFST+0,sp)
2474 02e6 2704 jreq L5721
2475 ; 884 bitstatus = SET;
2477 02e8 a601 ld a,#1
2479 02ea 2001 jra L7721
2480 02ec L5721:
2481 ; 888 bitstatus = RESET;
2483 02ec 4f clr a
2484 02ed L7721:
2485 ; 892 return((FlagStatus)bitstatus);
2489 02ed 5b05 addw sp,#5
2490 02ef 81 ret
2536 ; 913 ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT)
2536 ; 914 {
2537 switch .text
2538 02f0 _CLK_GetITStatus:
2540 02f0 88 push a
2541 02f1 88 push a
2542 00000001 OFST: set 1
2545 ; 916 ITStatus bitstatus = RESET;
2547 02f2 0f01 clr (OFST+0,sp)
2548 ; 919 assert_param(IS_CLK_IT_OK(CLK_IT));
2550 ; 921 if (CLK_IT == CLK_IT_SWIF)
2552 02f4 a11c cp a,#28
2553 02f6 2609 jrne L3231
2554 ; 924 if ((CLK->SWCR & (u8)CLK_IT) == (u8)0x0C)
2556 02f8 c450c5 and a,20677
2557 02fb a10c cp a,#12
2558 02fd 260f jrne L3331
2559 ; 926 bitstatus = SET;
2561 02ff 2009 jp LC006
2562 ; 930 bitstatus = RESET;
2563 0301 L3231:
2564 ; 936 if ((CLK->CSSR & (u8)CLK_IT) == (u8)0x0C)
2566 0301 c650c8 ld a,20680
2567 0304 1402 and a,(OFST+1,sp)
2568 0306 a10c cp a,#12
2569 0308 2604 jrne L3331
2570 ; 938 bitstatus = SET;
2572 030a LC006:
2574 030a a601 ld a,#1
2576 030c 2001 jra L1331
2577 030e L3331:
2578 ; 942 bitstatus = RESET;
2581 030e 4f clr a
2582 030f L1331:
2583 ; 947 return bitstatus;
2587 030f 85 popw x
2588 0310 81 ret
2624 ; 966 void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT)
2624 ; 967 {
2625 switch .text
2626 0311 _CLK_ClearITPendingBit:
2630 ; 970 assert_param(IS_CLK_IT_OK(CLK_IT));
2632 ; 972 if (CLK_IT == (u8)CLK_IT_CSSD)
2634 0311 a10c cp a,#12
2635 0313 2605 jrne L5531
2636 ; 975 CLK->CSSR &= (u8)(~CLK_CSSR_CSSD);
2638 0315 721750c8 bres 20680,#3
2641 0319 81 ret
2642 031a L5531:
2643 ; 980 CLK->SWCR &= (u8)(~CLK_SWCR_SWIF);
2645 031a 721750c5 bres 20677,#3
2646 ; 983 }
2649 031e 81 ret
2684 xdef _CLKPrescTable
2685 xdef _HSIDivFactor
2686 xdef _CLK_ClearITPendingBit
2687 xdef _CLK_GetITStatus
2688 xdef _CLK_GetFlagStatus
2689 xdef _CLK_GetSYSCLKSource
2690 xdef _CLK_GetClockFreq
2691 xdef _CLK_AdjustHSICalibrationValue
2692 xdef _CLK_SYSCLKEmergencyClear
2693 xdef _CLK_ClockSecuritySystemEnable
2694 xdef _CLK_CANConfig
2695 xdef _CLK_SWIMConfig
2696 xdef _CLK_SYSCLKConfig
2697 xdef _CLK_ITConfig
2698 xdef _CLK_CCOConfig
2699 xdef _CLK_HSIPrescalerConfig
2700 xdef _CLK_ClockSwitchConfig
2701 xdef _CLK_PeripheralClockConfig
2702 xdef _CLK_SlowActiveHaltWakeUpCmd
2703 xdef _CLK_FastHaltWakeUpCmd
2704 xdef _CLK_ClockSwitchCmd
2705 xdef _CLK_CCOCmd
2706 xdef _CLK_LSICmd
2707 xdef _CLK_HSICmd
2708 xdef _CLK_HSECmd
2709 xdef _CLK_DeInit
2710 xref.b c_lreg
2711 xref.b c_x
2730 xref c_ludv
2731 xref c_rtol
2732 xref c_ltor
2733 end
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