📄 stm8s_clk.ls
字号:
980 ; 409 u16 DownCounter = CLK_TIMEOUT;
982 00fe ae0491 ldw x,#1169
983 0101 1f03 ldw (OFST-1,sp),x
984 ; 410 ErrorStatus Swif = ERROR;
986 0103 7b02 ld a,(OFST-2,sp)
987 0105 97 ld xl,a
988 ; 413 assert_param(IS_CLK_SOURCE_OK(CLK_NewClock));
990 ; 414 assert_param(IS_CLK_SWITCHMODE_OK(CLK_SwitchMode));
992 ; 415 assert_param(IS_FUNCTIONALSTATE_OK(CLK_SwitchIT));
994 ; 416 assert_param(IS_CLK_CURRENTCLOCKSTATE_OK(CLK_CurrentClockState));
996 ; 419 clock_master = (CLK_Source_TypeDef)CLK->CMSR;
998 0106 c650c3 ld a,20675
999 0109 6b01 ld (OFST-3,sp),a
1000 ; 422 if (CLK_SwitchMode == CLK_SWITCHMODE_AUTO)
1002 010b 7b05 ld a,(OFST+1,sp)
1003 010d 4a dec a
1004 010e 262d jrne L734
1005 ; 426 CLK->SWCR |= CLK_SWCR_SWEN;
1007 0110 721250c5 bset 20677,#1
1008 ; 429 if (CLK_SwitchIT != DISABLE)
1010 0114 7b09 ld a,(OFST+5,sp)
1011 0116 2706 jreq L144
1012 ; 431 CLK->SWCR |= CLK_SWCR_SWIEN;
1014 0118 721450c5 bset 20677,#2
1016 011c 2004 jra L344
1017 011e L144:
1018 ; 435 CLK->SWCR &= (u8)(~CLK_SWCR_SWIEN);
1020 011e 721550c5 bres 20677,#2
1021 0122 L344:
1022 ; 439 CLK->SWR = (u8)CLK_NewClock;
1024 0122 7b06 ld a,(OFST+2,sp)
1025 0124 c750c4 ld 20676,a
1027 0127 2003 jra L154
1028 0129 L544:
1029 ; 443 DownCounter--;
1031 0129 5a decw x
1032 012a 1f03 ldw (OFST-1,sp),x
1033 012c L154:
1034 ; 441 while (((CLK->SWCR & CLK_SWCR_SWBSY) && (DownCounter != 0)))
1036 012c 720150c504 btjf 20677,#0,L554
1038 0131 1e03 ldw x,(OFST-1,sp)
1039 0133 26f4 jrne L544
1040 0135 L554:
1041 ; 446 if (DownCounter != 0)
1043 0135 1e03 ldw x,(OFST-1,sp)
1044 ; 448 Swif = SUCCESS;
1046 0137 2617 jrne LC003
1047 ; 452 Swif = ERROR;
1049 0139 0f02 clr (OFST-2,sp)
1050 013b 2017 jra L364
1051 013d L734:
1052 ; 460 if (CLK_SwitchIT != DISABLE)
1054 013d 7b09 ld a,(OFST+5,sp)
1055 013f 2706 jreq L564
1056 ; 462 CLK->SWCR |= CLK_SWCR_SWIEN;
1058 0141 721450c5 bset 20677,#2
1060 0145 2004 jra L764
1061 0147 L564:
1062 ; 466 CLK->SWCR &= (u8)(~CLK_SWCR_SWIEN);
1064 0147 721550c5 bres 20677,#2
1065 014b L764:
1066 ; 470 CLK->SWR = (u8)CLK_NewClock;
1068 014b 7b06 ld a,(OFST+2,sp)
1069 014d c750c4 ld 20676,a
1070 ; 474 Swif = SUCCESS;
1072 0150 LC003:
1074 0150 a601 ld a,#1
1075 0152 6b02 ld (OFST-2,sp),a
1076 0154 L364:
1077 ; 479 if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_HSI))
1079 0154 7b0a ld a,(OFST+6,sp)
1080 0156 260c jrne L174
1082 0158 7b01 ld a,(OFST-3,sp)
1083 015a a1e1 cp a,#225
1084 015c 2606 jrne L174
1085 ; 481 CLK->ICKR &= (u8)(~CLK_ICKR_HSIEN);
1087 015e 721150c0 bres 20672,#0
1089 0162 201e jra L374
1090 0164 L174:
1091 ; 483 else if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_LSI))
1093 0164 7b0a ld a,(OFST+6,sp)
1094 0166 260c jrne L574
1096 0168 7b01 ld a,(OFST-3,sp)
1097 016a a1d2 cp a,#210
1098 016c 2606 jrne L574
1099 ; 485 CLK->ICKR &= (u8)(~CLK_ICKR_LSIEN);
1101 016e 721750c0 bres 20672,#3
1103 0172 200e jra L374
1104 0174 L574:
1105 ; 487 else if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_HSE))
1107 0174 7b0a ld a,(OFST+6,sp)
1108 0176 260a jrne L374
1110 0178 7b01 ld a,(OFST-3,sp)
1111 017a a1b4 cp a,#180
1112 017c 2604 jrne L374
1113 ; 489 CLK->ECKR &= (u8)(~CLK_ECKR_HSEEN);
1115 017e 721150c1 bres 20673,#0
1116 0182 L374:
1117 ; 492 return(Swif);
1119 0182 7b02 ld a,(OFST-2,sp)
1122 0184 5b06 addw sp,#6
1123 0186 81 ret
1261 ; 509 void CLK_HSIPrescalerConfig(CLK_Prescaler_TypeDef HSIPrescaler)
1261 ; 510 {
1262 switch .text
1263 0187 _CLK_HSIPrescalerConfig:
1265 0187 88 push a
1266 00000000 OFST: set 0
1269 ; 513 assert_param(IS_CLK_HSIPRESCALER_OK(HSIPrescaler));
1271 ; 516 CLK->CKDIVR &= (u8)(~CLK_CKDIVR_HSIDIV);
1273 0188 c650c6 ld a,20678
1274 018b a4e7 and a,#231
1275 018d c750c6 ld 20678,a
1276 ; 519 CLK->CKDIVR |= (u8)HSIPrescaler;
1278 0190 c650c6 ld a,20678
1279 0193 1a01 or a,(OFST+1,sp)
1280 0195 c750c6 ld 20678,a
1281 ; 521 }
1284 0198 84 pop a
1285 0199 81 ret
1420 ; 539 void CLK_CCOConfig(CLK_Output_TypeDef CLK_CCO)
1420 ; 540 {
1421 switch .text
1422 019a _CLK_CCOConfig:
1424 019a 88 push a
1425 00000000 OFST: set 0
1428 ; 543 assert_param(IS_CLK_OUTPUT_OK(CLK_CCO));
1430 ; 546 CLK->CCOR &= (u8)(~CLK_CCOR_CCOSEL);
1432 019b c650c9 ld a,20681
1433 019e a4e1 and a,#225
1434 01a0 c750c9 ld 20681,a
1435 ; 549 CLK->CCOR |= (u8)CLK_CCO;
1437 01a3 c650c9 ld a,20681
1438 01a6 1a01 or a,(OFST+1,sp)
1439 01a8 c750c9 ld 20681,a
1440 ; 552 CLK->CCOR |= CLK_CCOR_CCOEN;
1442 ; 554 }
1445 01ab 84 pop a
1446 01ac 721050c9 bset 20681,#0
1447 01b0 81 ret
1512 ; 571 void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState IT_NewState)
1512 ; 572 {
1513 switch .text
1514 01b1 _CLK_ITConfig:
1516 01b1 89 pushw x
1517 00000000 OFST: set 0
1520 ; 575 assert_param(IS_FUNCTIONALSTATE_OK(IT_NewState));
1522 ; 576 assert_param(IS_CLK_IT_OK(CLK_IT));
1524 ; 578 if (IT_NewState != DISABLE)
1526 01b2 9f ld a,xl
1527 01b3 4d tnz a
1528 01b4 2715 jreq L776
1529 ; 580 switch (CLK_IT)
1531 01b6 9e ld a,xh
1533 ; 588 default:
1533 ; 589 break;
1534 01b7 a00c sub a,#12
1535 01b9 270a jreq L336
1536 01bb a010 sub a,#16
1537 01bd 2620 jrne L507
1538 ; 582 case CLK_IT_SWIF: /* Enable the clock switch interrupt */
1538 ; 583 CLK->SWCR |= CLK_SWCR_SWIEN;
1540 01bf 721450c5 bset 20677,#2
1541 ; 584 break;
1543 01c3 201a jra L507
1544 01c5 L336:
1545 ; 585 case CLK_IT_CSSD: /* Enable the clock security system detection interrupt */
1545 ; 586 CLK->CSSR |= CLK_CSSR_CSSDIE;
1547 01c5 721450c8 bset 20680,#2
1548 ; 587 break;
1550 01c9 2014 jra L507
1551 ; 588 default:
1551 ; 589 break;
1554 01cb L776:
1555 ; 594 switch (CLK_IT)
1557 01cb 7b01 ld a,(OFST+1,sp)
1559 ; 602 default:
1559 ; 603 break;
1560 01cd a00c sub a,#12
1561 01cf 270a jreq L146
1562 01d1 a010 sub a,#16
1563 01d3 260a jrne L507
1564 ; 596 case CLK_IT_SWIF: /* Disable the clock switch interrupt */
1564 ; 597 CLK->SWCR &= (u8)(~CLK_SWCR_SWIEN);
1566 01d5 721550c5 bres 20677,#2
1567 ; 598 break;
1569 01d9 2004 jra L507
1570 01db L146:
1571 ; 599 case CLK_IT_CSSD: /* Disable the clock security system detection interrupt */
1571 ; 600 CLK->CSSR &= (u8)(~CLK_CSSR_CSSDIE);
1573 01db 721550c8 bres 20680,#2
1574 ; 601 break;
1575 01df L507:
1576 ; 607 }
1579 01df 85 popw x
1580 01e0 81 ret
1581 ; 602 default:
1581 ; 603 break;
1617 ; 623 void CLK_SYSCLKConfig(CLK_Prescaler_TypeDef ClockPrescaler)
1617 ; 624 {
1618 switch .text
1619 01e1 _CLK_SYSCLKConfig:
1621 01e1 88 push a
1622 00000000 OFST: set 0
1625 ; 627 assert_param(IS_CLK_PRESCALER_OK(ClockPrescaler));
1627 ; 629 if (((u8)ClockPrescaler & (u8)0x80) == 0x00) /* Bit7 = 0 means HSI divider */
1629 01e2 a580 bcp a,#128
1630 01e4 260e jrne L137
1631 ; 631 CLK->CKDIVR &= (u8)(~CLK_CKDIVR_HSIDIV);
1633 01e6 c650c6 ld a,20678
1634 01e9 a4e7 and a,#231
1635 01eb c750c6 ld 20678,a
1636 ; 632 CLK->CKDIVR |= (u8)((u8)ClockPrescaler & (u8)CLK_CKDIVR_HSIDIV);
1638 01ee 7b01 ld a,(OFST+1,sp)
1639 01f0 a418 and a,#24
1641 01f2 200c jra L337
1642 01f4 L137:
1643 ; 636 CLK->CKDIVR &= (u8)(~CLK_CKDIVR_CPUDIV);
1645 01f4 c650c6 ld a,20678
1646 01f7 a4f8 and a,#248
1647 01f9 c750c6 ld 20678,a
1648 ; 637 CLK->CKDIVR |= (u8)((u8)ClockPrescaler & (u8)CLK_CKDIVR_CPUDIV);
1650 01fc 7b01 ld a,(OFST+1,sp)
1651 01fe a407 and a,#7
1652 0200 L337:
1653 0200 ca50c6 or a,20678
1654 0203 c750c6 ld 20678,a
1655 ; 640 }
1658 0206 84 pop a
1659 0207 81 ret
1715 ; 654 void CLK_SWIMConfig(CLK_SWIMDivider_TypeDef CLK_SWIMDivider)
1715 ; 655 {
1716 switch .text
1717 0208 _CLK_SWIMConfig:
1721 ; 658 assert_param(IS_CLK_SWIMDIVIDER_OK(CLK_SWIMDivider));
1723 ; 660 if (CLK_SWIMDivider != CLK_SWIMDIVIDER_2)
1725 0208 4d tnz a
1726 0209 2705 jreq L367
1727 ; 663 CLK->SWIMCCR |= CLK_SWIMCCR_SWIMDIV;
1729 020b 721050cd bset 20685,#0
1732 020f 81 ret
1733 0210 L367:
1734 ; 668 CLK->SWIMCCR &= (u8)(~CLK_SWIMCCR_SWIMDIV);
1736 0210 721150cd bres 20685,#0
1737 ; 671 }
1740 0214 81 ret
1837 ; 686 void CLK_CANConfig(CLK_CANDivider_TypeDef CLK_CANDivider)
1837 ; 687 {
1838 switch .text
1839 0215 _CLK_CANConfig:
1841 0215 88 push a
1842 00000000 OFST: set 0
1845 ; 690 assert_param(IS_CLK_CANDIVIDER_OK(CLK_CANDivider));
1847 ; 693 CLK->CANCCR &= (u8)(~CLK_CANCCR_CANDIV);
1849 0216 c650cb ld a,20683
1850 0219 a4f8 and a,#248
1851 021b c750cb ld 20683,a
1852 ; 696 CLK->CANCCR |= (u8)CLK_CANDivider;
1854 021e c650cb ld a,20683
1855 0221 1a01 or a,(OFST+1,sp)
1856 0223 c750cb ld 20683,a
1857 ; 698 }
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