📄 stm8s_clk.ls
字号:
1 ; C Compiler for STM8 (COSMIC Software)
2 ; Generator V4.2.8 - 03 Dec 2008
3 ; Optimizer V4.2.8 - 03 Dec 2008
5 .const: section .text
6 0000 _HSIDivFactor:
7 0000 01 dc.b 1
8 0001 02 dc.b 2
9 0002 04 dc.b 4
10 0003 08 dc.b 8
11 0004 _CLKPrescTable:
12 0004 01 dc.b 1
13 0005 02 dc.b 2
14 0006 04 dc.b 4
15 0007 08 dc.b 8
16 0008 0a dc.b 10
17 0009 10 dc.b 16
18 000a 14 dc.b 20
19 000b 28 dc.b 40
48 ; 83 void CLK_DeInit(void)
48 ; 84 {
50 switch .text
51 0000 _CLK_DeInit:
55 ; 86 CLK->ICKR = CLK_ICKR_RESET_VALUE;
57 0000 350150c0 mov 20672,#1
58 ; 87 CLK->ECKR = CLK_ECKR_RESET_VALUE;
60 0004 725f50c1 clr 20673
61 ; 88 CLK->SWR = CLK_SWR_RESET_VALUE;
63 0008 35e150c4 mov 20676,#225
64 ; 89 CLK->SWCR = CLK_SWCR_RESET_VALUE;
66 000c 725f50c5 clr 20677
67 ; 90 CLK->CKDIVR = CLK_CKDIVR_RESET_VALUE;
69 0010 351850c6 mov 20678,#24
70 ; 91 CLK->PCKENR1 = CLK_PCKENR1_RESET_VALUE;
72 0014 35ff50c7 mov 20679,#255
73 ; 92 CLK->PCKENR2 = CLK_PCKENR2_RESET_VALUE;
75 0018 35ff50ca mov 20682,#255
76 ; 93 CLK->CSSR = CLK_CSSR_RESET_VALUE;
78 001c 725f50c8 clr 20680
79 ; 95 CLK->CCOR = CLK_CCOR_RESET_VALUE;
81 0020 725f50c9 clr 20681
83 0024 L52:
84 ; 96 while (CLK->CCOR & CLK_CCOR_CCOEN)
86 0024 720050c9fb btjt 20681,#0,L52
87 ; 98 CLK->CCOR = CLK_CCOR_RESET_VALUE;
89 0029 725f50c9 clr 20681
90 ; 100 CLK->CANCCR = CLK_CANCCR_RESET_VALUE;
92 002d 725f50cb clr 20683
93 ; 101 CLK->HSITRIMR = CLK_HSITRIMR_RESET_VALUE;
95 0031 725f50cc clr 20684
96 ; 102 CLK->SWIMCCR = CLK_SWIMCCR_RESET_VALUE;
98 0035 725f50cd clr 20685
99 ; 104 }
102 0039 81 ret
158 ; 123 void CLK_FastHaltWakeUpCmd(FunctionalState NewState)
158 ; 124 {
159 switch .text
160 003a _CLK_FastHaltWakeUpCmd:
164 ; 127 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
166 ; 129 if (NewState != DISABLE)
168 003a 4d tnz a
169 003b 2705 jreq L75
170 ; 132 CLK->ICKR |= CLK_ICKR_FHWU;
172 003d 721450c0 bset 20672,#2
175 0041 81 ret
176 0042 L75:
177 ; 137 CLK->ICKR &= (u8)(~CLK_ICKR_FHWU);
179 0042 721550c0 bres 20672,#2
180 ; 140 }
183 0046 81 ret
218 ; 154 void CLK_HSECmd(FunctionalState CLK_NewState)
218 ; 155 {
219 switch .text
220 0047 _CLK_HSECmd:
224 ; 158 assert_param(IS_FUNCTIONALSTATE_OK(CLK_NewState));
226 ; 160 if (CLK_NewState != DISABLE)
228 0047 4d tnz a
229 0048 2705 jreq L101
230 ; 163 CLK->ECKR |= CLK_ECKR_HSEEN;
232 004a 721050c1 bset 20673,#0
235 004e 81 ret
236 004f L101:
237 ; 168 CLK->ECKR &= (u8)(~CLK_ECKR_HSEEN);
239 004f 721150c1 bres 20673,#0
240 ; 171 }
243 0053 81 ret
278 ; 185 void CLK_HSICmd(FunctionalState CLK_NewState)
278 ; 186 {
279 switch .text
280 0054 _CLK_HSICmd:
284 ; 189 assert_param(IS_FUNCTIONALSTATE_OK(CLK_NewState));
286 ; 191 if (CLK_NewState != DISABLE)
288 0054 4d tnz a
289 0055 2705 jreq L321
290 ; 194 CLK->ICKR |= CLK_ICKR_HSIEN;
292 0057 721050c0 bset 20672,#0
295 005b 81 ret
296 005c L321:
297 ; 199 CLK->ICKR &= (u8)(~CLK_ICKR_HSIEN);
299 005c 721150c0 bres 20672,#0
300 ; 202 }
303 0060 81 ret
338 ; 216 void CLK_LSICmd(FunctionalState CLK_NewState)
338 ; 217 {
339 switch .text
340 0061 _CLK_LSICmd:
344 ; 220 assert_param(IS_FUNCTIONALSTATE_OK(CLK_NewState));
346 ; 222 if (CLK_NewState != DISABLE)
348 0061 4d tnz a
349 0062 2705 jreq L541
350 ; 225 CLK->ICKR |= CLK_ICKR_LSIEN;
352 0064 721650c0 bset 20672,#3
355 0068 81 ret
356 0069 L541:
357 ; 230 CLK->ICKR &= (u8)(~CLK_ICKR_LSIEN);
359 0069 721750c0 bres 20672,#3
360 ; 233 }
363 006d 81 ret
398 ; 248 void CLK_CCOCmd(FunctionalState CLK_NewState)
398 ; 249 {
399 switch .text
400 006e _CLK_CCOCmd:
404 ; 252 assert_param(IS_FUNCTIONALSTATE_OK(CLK_NewState));
406 ; 254 if (CLK_NewState != DISABLE)
408 006e 4d tnz a
409 006f 2705 jreq L761
410 ; 257 CLK->CCOR |= CLK_CCOR_CCOEN;
412 0071 721050c9 bset 20681,#0
415 0075 81 ret
416 0076 L761:
417 ; 262 CLK->CCOR &= (u8)(~CLK_CCOR_CCOEN);
419 0076 721150c9 bres 20681,#0
420 ; 265 }
423 007a 81 ret
458 ; 281 void CLK_ClockSwitchCmd(FunctionalState CLK_NewState)
458 ; 282 {
459 switch .text
460 007b _CLK_ClockSwitchCmd:
464 ; 285 assert_param(IS_FUNCTIONALSTATE_OK(CLK_NewState));
466 ; 287 if (CLK_NewState != DISABLE )
468 007b 4d tnz a
469 007c 2705 jreq L112
470 ; 290 CLK->SWCR |= CLK_SWCR_SWEN;
472 007e 721250c5 bset 20677,#1
475 0082 81 ret
476 0083 L112:
477 ; 295 CLK->SWCR &= (u8)(~CLK_SWCR_SWEN);
479 0083 721350c5 bres 20677,#1
480 ; 298 }
483 0087 81 ret
519 ; 315 void CLK_SlowActiveHaltWakeUpCmd(FunctionalState NewState)
519 ; 316 {
520 switch .text
521 0088 _CLK_SlowActiveHaltWakeUpCmd:
525 ; 319 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
527 ; 321 if (NewState != DISABLE)
529 0088 4d tnz a
530 0089 2705 jreq L332
531 ; 324 CLK->ICKR |= CLK_ICKR_SWUAH;
533 008b 721a50c0 bset 20672,#5
536 008f 81 ret
537 0090 L332:
538 ; 329 CLK->ICKR &= (u8)(~CLK_ICKR_SWUAH);
540 0090 721b50c0 bres 20672,#5
541 ; 332 }
544 0094 81 ret
679 ; 349 void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState CLK_NewState)
679 ; 350 {
680 switch .text
681 0095 _CLK_PeripheralClockConfig:
683 0095 89 pushw x
684 00000000 OFST: set 0
687 ; 353 assert_param(IS_FUNCTIONALSTATE_OK(CLK_NewState));
689 ; 354 assert_param(IS_CLK_PERIPHERAL_OK(CLK_Peripheral));
691 ; 356 if (((u8)CLK_Peripheral & (u8)0x10) == 0x00)
693 0096 9e ld a,xh
694 0097 a510 bcp a,#16
695 0099 2630 jrne L313
696 ; 358 if (CLK_NewState != DISABLE)
698 009b 7b02 ld a,(OFST+2,sp)
699 009d 2714 jreq L513
700 ; 361 CLK->PCKENR1 |= (u8)((u8)1 << ((u8)CLK_Peripheral & (u8)0x0F));
702 009f 7b01 ld a,(OFST+1,sp)
703 00a1 a40f and a,#15
704 00a3 5f clrw x
705 00a4 97 ld xl,a
706 00a5 a601 ld a,#1
707 00a7 5d tnzw x
708 00a8 2704 jreq L62
709 00aa L03:
710 00aa 48 sll a
711 00ab 5a decw x
712 00ac 26fc jrne L03
713 00ae L62:
714 00ae ca50c7 or a,20679
716 00b1 2013 jp LC002
717 00b3 L513:
718 ; 366 CLK->PCKENR1 &= (u8)(~(u8)(((u8)1 << ((u8)CLK_Peripheral & (u8)0x0F))));
720 00b3 7b01 ld a,(OFST+1,sp)
721 00b5 a40f and a,#15
722 00b7 5f clrw x
723 00b8 97 ld xl,a
724 00b9 a601 ld a,#1
725 00bb 5d tnzw x
726 00bc 2704 jreq L23
727 00be L43:
728 00be 48 sll a
729 00bf 5a decw x
730 00c0 26fc jrne L43
731 00c2 L23:
732 00c2 43 cpl a
733 00c3 c450c7 and a,20679
734 00c6 LC002:
735 00c6 c750c7 ld 20679,a
736 00c9 202e jra L123
737 00cb L313:
738 ; 371 if (CLK_NewState != DISABLE)
740 00cb 7b02 ld a,(OFST+2,sp)
741 00cd 2714 jreq L323
742 ; 374 CLK->PCKENR2 |= (u8)((u8)1 << ((u8)CLK_Peripheral & (u8)0x0F));
744 00cf 7b01 ld a,(OFST+1,sp)
745 00d1 a40f and a,#15
746 00d3 5f clrw x
747 00d4 97 ld xl,a
748 00d5 a601 ld a,#1
749 00d7 5d tnzw x
750 00d8 2704 jreq L63
751 00da L04:
752 00da 48 sll a
753 00db 5a decw x
754 00dc 26fc jrne L04
755 00de L63:
756 00de ca50ca or a,20682
758 00e1 2013 jp LC001
759 00e3 L323:
760 ; 379 CLK->PCKENR2 &= (u8)(~(u8)(((u8)1 << ((u8)CLK_Peripheral & (u8)0x0F))));
762 00e3 7b01 ld a,(OFST+1,sp)
763 00e5 a40f and a,#15
764 00e7 5f clrw x
765 00e8 97 ld xl,a
766 00e9 a601 ld a,#1
767 00eb 5d tnzw x
768 00ec 2704 jreq L24
769 00ee L44:
770 00ee 48 sll a
771 00ef 5a decw x
772 00f0 26fc jrne L44
773 00f2 L24:
774 00f2 43 cpl a
775 00f3 c450ca and a,20682
776 00f6 LC001:
777 00f6 c750ca ld 20682,a
778 00f9 L123:
779 ; 383 }
782 00f9 85 popw x
783 00fa 81 ret
971 ; 405 ErrorStatus CLK_ClockSwitchConfig(CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState CLK_SwitchIT, CLK_CurrentClockState_TypeDef CLK_CurrentClockState)
971 ; 406 {
972 switch .text
973 00fb _CLK_ClockSwitchConfig:
975 00fb 89 pushw x
976 00fc 5204 subw sp,#4
977 00000004 OFST: set 4
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