📄 stm8s_tim4.ls
字号:
1 ; C Compiler for STM8 (COSMIC Software)
2 ; Generator V4.2.8 - 03 Dec 2008
3 ; Optimizer V4.2.8 - 03 Dec 2008
33 ; 60 void TIM4_DeInit(void)
33 ; 61 {
35 switch .text
36 0000 _TIM4_DeInit:
40 ; 62 TIM4->CR1 = TIM4_CR1_RESET_VALUE;
42 0000 725f5340 clr 21312
43 ; 63 TIM4->IER = TIM4_IER_RESET_VALUE;
45 0004 725f5341 clr 21313
46 ; 64 TIM4->CNTR = TIM4_CNTR_RESET_VALUE;
48 0008 725f5344 clr 21316
49 ; 65 TIM4->PSCR = TIM4_PSCR_RESET_VALUE;
51 000c 725f5345 clr 21317
52 ; 66 TIM4->ARR = TIM4_ARR_RESET_VALUE;
54 0010 35ff5346 mov 21318,#255
55 ; 67 TIM4->SR1 = TIM4_SR1_RESET_VALUE;
57 0014 725f5342 clr 21314
58 ; 68 }
61 0018 81 ret
167 ; 87 void TIM4_TimeBaseInit(TIM4_Prescaler_TypeDef TIM4_Prescaler, u8 TIM4_Period)
167 ; 88 {
168 switch .text
169 0019 _TIM4_TimeBaseInit:
173 ; 90 assert_param(IS_TIM4_PRESCALER_OK(TIM4_Prescaler));
175 ; 92 TIM4->PSCR = (u8)(TIM4_Prescaler);
177 0019 9e ld a,xh
178 001a c75345 ld 21317,a
179 ; 94 TIM4->ARR = (u8)(TIM4_Period);
181 001d 9f ld a,xl
182 001e c75346 ld 21318,a
183 ; 95 }
186 0021 81 ret
241 ; 114 void TIM4_Cmd(FunctionalState NewState)
241 ; 115 {
242 switch .text
243 0022 _TIM4_Cmd:
247 ; 117 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
249 ; 120 if (NewState != DISABLE)
251 0022 4d tnz a
252 0023 2705 jreq L511
253 ; 122 TIM4->CR1 |= TIM4_CR1_CEN;
255 0025 72105340 bset 21312,#0
258 0029 81 ret
259 002a L511:
260 ; 126 TIM4->CR1 &= (u8)(~TIM4_CR1_CEN);
262 002a 72115340 bres 21312,#0
263 ; 128 }
266 002e 81 ret
324 ; 149 void TIM4_ITConfig(TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState)
324 ; 150 {
325 switch .text
326 002f _TIM4_ITConfig:
328 002f 89 pushw x
329 00000000 OFST: set 0
332 ; 152 assert_param(IS_TIM4_IT_OK(TIM4_IT));
334 ; 153 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
336 ; 155 if (NewState != DISABLE)
338 0030 9f ld a,xl
339 0031 4d tnz a
340 0032 2706 jreq L151
341 ; 158 TIM4->IER |= TIM4_IT;
343 0034 9e ld a,xh
344 0035 ca5341 or a,21313
346 0038 2006 jra L351
347 003a L151:
348 ; 163 TIM4->IER &= (u8)(~TIM4_IT);
350 003a 7b01 ld a,(OFST+1,sp)
351 003c 43 cpl a
352 003d c45341 and a,21313
353 0040 L351:
354 0040 c75341 ld 21313,a
355 ; 165 }
358 0043 85 popw x
359 0044 81 ret
395 ; 182 void TIM4_UpdateDisableConfig(FunctionalState NewState)
395 ; 183 {
396 switch .text
397 0045 _TIM4_UpdateDisableConfig:
401 ; 185 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
403 ; 188 if (NewState != DISABLE)
405 0045 4d tnz a
406 0046 2705 jreq L371
407 ; 190 TIM4->CR1 |= TIM4_CR1_UDIS;
409 0048 72125340 bset 21312,#1
412 004c 81 ret
413 004d L371:
414 ; 194 TIM4->CR1 &= (u8)(~TIM4_CR1_UDIS);
416 004d 72135340 bres 21312,#1
417 ; 196 }
420 0051 81 ret
478 ; 215 void TIM4_UpdateRequestConfig(TIM4_UpdateSource_TypeDef TIM4_UpdateSource)
478 ; 216 {
479 switch .text
480 0052 _TIM4_UpdateRequestConfig:
484 ; 218 assert_param(IS_TIM4_UPDATE_SOURCE_OK(TIM4_UpdateSource));
486 ; 221 if (TIM4_UpdateSource != TIM4_UPDATESOURCE_GLOBAL)
488 0052 4d tnz a
489 0053 2705 jreq L522
490 ; 223 TIM4->CR1 |= TIM4_CR1_URS;
492 0055 72145340 bset 21312,#2
495 0059 81 ret
496 005a L522:
497 ; 227 TIM4->CR1 &= (u8)(~TIM4_CR1_URS);
499 005a 72155340 bres 21312,#2
500 ; 229 }
503 005e 81 ret
560 ; 248 void TIM4_SelectOnePulseMode(TIM4_OPMode_TypeDef TIM4_OPMode)
560 ; 249 {
561 switch .text
562 005f _TIM4_SelectOnePulseMode:
566 ; 251 assert_param(IS_TIM4_OPM_MODE_OK(TIM4_OPMode));
568 ; 254 if (TIM4_OPMode != TIM4_OPMODE_REPETITIVE)
570 005f 4d tnz a
571 0060 2705 jreq L752
572 ; 256 TIM4->CR1 |= TIM4_CR1_OPM;
574 0062 72165340 bset 21312,#3
577 0066 81 ret
578 0067 L752:
579 ; 260 TIM4->CR1 &= (u8)(~TIM4_CR1_OPM);
581 0067 72175340 bres 21312,#3
582 ; 263 }
585 006b 81 ret
653 ; 294 void TIM4_PrescalerConfig(TIM4_Prescaler_TypeDef Prescaler, TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode)
653 ; 295 {
654 switch .text
655 006c _TIM4_PrescalerConfig:
659 ; 297 assert_param(IS_TIM4_PRESCALER_RELOAD_OK(TIM4_PSCReloadMode));
661 ; 298 assert_param(IS_TIM4_PRESCALER_OK(Prescaler));
663 ; 301 TIM4->PSCR = Prescaler;
665 006c 9e ld a,xh
666 006d c75345 ld 21317,a
667 ; 304 TIM4->EGR = TIM4_PSCReloadMode;
669 0070 9f ld a,xl
670 0071 c75343 ld 21315,a
671 ; 305 }
674 0074 81 ret
710 ; 322 void TIM4_ARRPreloadConfig(FunctionalState NewState)
710 ; 323 {
711 switch .text
712 0075 _TIM4_ARRPreloadConfig:
716 ; 325 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
718 ; 328 if (NewState != DISABLE)
720 0075 4d tnz a
721 0076 2705 jreq L333
722 ; 330 TIM4->CR1 |= TIM4_CR1_ARPE;
724 0078 721e5340 bset 21312,#7
727 007c 81 ret
728 007d L333:
729 ; 334 TIM4->CR1 &= (u8)(~TIM4_CR1_ARPE);
731 007d 721f5340 bres 21312,#7
732 ; 336 }
735 0081 81 ret
784 ; 354 void TIM4_GenerateEvent(TIM4_EventSource_TypeDef TIM4_EventSource)
784 ; 355 {
785 switch .text
786 0082 _TIM4_GenerateEvent:
790 ; 357 assert_param(IS_TIM4_EVENT_SOURCE_OK(TIM4_EventSource));
792 ; 360 TIM4->EGR = (u8)(TIM4_EventSource);
794 0082 c75343 ld 21315,a
795 ; 361 }
798 0085 81 ret
832 ; 379 void TIM4_SetCounter(u8 Counter)
832 ; 380 {
833 switch .text
834 0086 _TIM4_SetCounter:
838 ; 382 TIM4->CNTR = (u8)(Counter);
840 0086 c75344 ld 21316,a
841 ; 383 }
844 0089 81 ret
878 ; 401 void TIM4_SetAutoreload(u8 Autoreload)
878 ; 402 {
879 switch .text
880 008a _TIM4_SetAutoreload:
884 ; 404 TIM4->ARR = (u8)(Autoreload);
886 008a c75346 ld 21318,a
887 ; 405 }
890 008d 81 ret
913 ; 423 u8 TIM4_GetCounter(void)
913 ; 424 {
914 switch .text
915 008e _TIM4_GetCounter:
919 ; 426 return (u8)(TIM4->CNTR);
921 008e c65344 ld a,21316
924 0091 81 ret
948 ; 445 TIM4_Prescaler_TypeDef TIM4_GetPrescaler(void)
948 ; 446 {
949 switch .text
950 0092 _TIM4_GetPrescaler:
954 ; 448 return (TIM4_Prescaler_TypeDef)(TIM4->PSCR);
956 0092 c65345 ld a,21317
959 0095 81 ret
1028 ; 468 FlagStatus TIM4_GetFlagStatus(TIM4_FLAG_TypeDef TIM4_FLAG)
1028 ; 469 {
1029 switch .text
1030 0096 _TIM4_GetFlagStatus:
1034 ; 471 assert_param(IS_TIM4_GET_FLAG_OK(TIM4_FLAG));
1036 ; 473 if ((TIM4->SR1 & TIM4_FLAG) != RESET )
1038 0096 c45342 and a,21314
1039 0099 2702 jreq L374
1040 ; 475 return (FlagStatus)(SET);
1042 009b a601 ld a,#1
1045 009d L374:
1046 ; 479 return (FlagStatus)(RESET);
1050 009d 81 ret
1085 ; 499 void TIM4_ClearFlag(TIM4_FLAG_TypeDef TIM4_FLAG)
1085 ; 500 {
1086 switch .text
1087 009e _TIM4_ClearFlag:
1091 ; 502 assert_param(IS_TIM4_GET_FLAG_OK(TIM4_FLAG));
1093 ; 505 TIM4->SR1 = (u8)(~TIM4_FLAG);
1095 009e 43 cpl a
1096 009f c75342 ld 21314,a
1097 ; 507 }
1100 00a2 81 ret
1136 ; 526 ITStatus TIM4_GetITStatus(TIM4_IT_TypeDef TIM4_IT)
1136 ; 527 {
1137 switch .text
1138 00a3 _TIM4_GetITStatus:
1140 00a3 88 push a
1141 00000000 OFST: set 0
1144 ; 529 assert_param(IS_TIM4_IT_OK(TIM4_IT));
1146 ; 531 if (((TIM4->SR1 & TIM4_IT) != RESET ) && ((TIM4->IER & TIM4_IT) != RESET ))
1148 00a4 c45342 and a,21314
1149 00a7 270c jreq L335
1151 00a9 c65341 ld a,21313
1152 00ac 1501 bcp a,(OFST+1,sp)
1153 00ae 2705 jreq L335
1154 ; 533 return (ITStatus)(SET);
1156 00b0 a601 ld a,#1
1159 00b2 5b01 addw sp,#1
1160 00b4 81 ret
1161 00b5 L335:
1162 ; 537 return (ITStatus)(RESET);
1164 00b5 4f clr a
1167 00b6 5b01 addw sp,#1
1168 00b8 81 ret
1204 ; 557 void TIM4_ClearITPendingBit(TIM4_IT_TypeDef TIM4_IT)
1204 ; 558 {
1205 switch .text
1206 00b9 _TIM4_ClearITPendingBit:
1210 ; 560 assert_param(IS_TIM4_IT_OK(TIM4_IT));
1212 ; 563 TIM4->SR1 = (u8)(~TIM4_IT);
1214 00b9 43 cpl a
1215 00ba c75342 ld 21314,a
1216 ; 564 }
1219 00bd 81 ret
1232 xdef _TIM4_ClearITPendingBit
1233 xdef _TIM4_GetITStatus
1234 xdef _TIM4_ClearFlag
1235 xdef _TIM4_GetFlagStatus
1236 xdef _TIM4_GetPrescaler
1237 xdef _TIM4_GetCounter
1238 xdef _TIM4_SetAutoreload
1239 xdef _TIM4_SetCounter
1240 xdef _TIM4_GenerateEvent
1241 xdef _TIM4_ARRPreloadConfig
1242 xdef _TIM4_PrescalerConfig
1243 xdef _TIM4_SelectOnePulseMode
1244 xdef _TIM4_UpdateRequestConfig
1245 xdef _TIM4_UpdateDisableConfig
1246 xdef _TIM4_ITConfig
1247 xdef _TIM4_Cmd
1248 xdef _TIM4_TimeBaseInit
1249 xdef _TIM4_DeInit
1268 end
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