📄 stm8s_adc1.ls
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2092 0287 2704 jreq L221
2093 0289 L421:
2094 0289 48 sll a
2095 028a 5a decw x
2096 028b 26fc jrne L421
2097 028d L221:
2098 028d c4540c and a,21516
2099 0290 L7201:
2100 ; 706 return ((FlagStatus)status);
2104 0290 85 popw x
2105 0291 81 ret
2256 ; 725 FlagStatus ADC1_GetFlagStatus(ADC1_Flag_TypeDef Flag)
2256 ; 726 {
2257 switch .text
2258 0292 _ADC1_GetFlagStatus:
2260 0292 88 push a
2261 0293 88 push a
2262 00000001 OFST: set 1
2265 ; 727 u8 flagstatus = 0;
2267 ; 728 u8 temp = 0;
2269 ; 731 assert_param(IS_ADC1_FLAG_OK(Flag));
2271 ; 733 if ((Flag & 0x0F) == 0x01)
2273 0294 7b02 ld a,(OFST+1,sp)
2274 0296 a40f and a,#15
2275 0298 4a dec a
2276 0299 2607 jrne L5111
2277 ; 736 flagstatus = (u8)(ADC1->CR3 & ADC1_CR3_OVR);
2279 029b c65403 ld a,21507
2280 029e a440 and a,#64
2282 02a0 2039 jra L7111
2283 02a2 L5111:
2284 ; 738 else if ((Flag & 0xF0) == 0x10)
2286 02a2 7b02 ld a,(OFST+1,sp)
2287 02a4 a4f0 and a,#240
2288 02a6 a110 cp a,#16
2289 02a8 262c jrne L1211
2290 ; 741 temp = (u8)(Flag & 0x0F);
2292 02aa 7b02 ld a,(OFST+1,sp)
2293 02ac a40f and a,#15
2294 02ae 6b01 ld (OFST+0,sp),a
2295 ; 742 if (temp < 8)
2297 02b0 a108 cp a,#8
2298 02b2 2410 jruge L3211
2299 ; 744 flagstatus = (u8)(ADC1->AWSRL & (1 << temp));
2301 02b4 5f clrw x
2302 02b5 97 ld xl,a
2303 02b6 a601 ld a,#1
2304 02b8 5d tnzw x
2305 02b9 2704 jreq L031
2306 02bb L231:
2307 02bb 48 sll a
2308 02bc 5a decw x
2309 02bd 26fc jrne L231
2310 02bf L031:
2311 02bf c4540d and a,21517
2313 02c2 2017 jra L7111
2314 02c4 L3211:
2315 ; 748 flagstatus = (u8)(ADC1->AWSRH & (1 << (temp - 8)));
2317 02c4 a008 sub a,#8
2318 02c6 5f clrw x
2319 02c7 97 ld xl,a
2320 02c8 a601 ld a,#1
2321 02ca 5d tnzw x
2322 02cb 2704 jreq L431
2323 02cd L631:
2324 02cd 48 sll a
2325 02ce 5a decw x
2326 02cf 26fc jrne L631
2327 02d1 L431:
2328 02d1 c4540c and a,21516
2329 02d4 2005 jra L7111
2330 02d6 L1211:
2331 ; 753 flagstatus = (u8)(ADC1->CSR & Flag);
2333 02d6 c65400 ld a,21504
2334 02d9 1402 and a,(OFST+1,sp)
2335 02db L7111:
2336 ; 755 return ((FlagStatus)flagstatus);
2340 02db 85 popw x
2341 02dc 81 ret
2385 ; 774 void ADC1_ClearFlag(ADC1_Flag_TypeDef Flag)
2385 ; 775 {
2386 switch .text
2387 02dd _ADC1_ClearFlag:
2389 02dd 88 push a
2390 02de 88 push a
2391 00000001 OFST: set 1
2394 ; 776 u8 temp = 0;
2396 02df 0f01 clr (OFST+0,sp)
2397 ; 779 assert_param(IS_ADC1_FLAG_OK(Flag));
2399 ; 781 if ((Flag & 0x0F) == 0x01)
2401 02e1 a40f and a,#15
2402 02e3 4a dec a
2403 02e4 2606 jrne L3511
2404 ; 784 ADC1->CR3 &= (u8)(~ADC1_CR3_OVR);
2406 02e6 721d5403 bres 21507,#6
2408 02ea 2045 jra L5511
2409 02ec L3511:
2410 ; 786 else if ((Flag & 0xF0) == 0x10)
2412 02ec 7b02 ld a,(OFST+1,sp)
2413 02ee a4f0 and a,#240
2414 02f0 a110 cp a,#16
2415 02f2 2634 jrne L7511
2416 ; 789 temp = (u8)(Flag & 0x0F);
2418 02f4 7b02 ld a,(OFST+1,sp)
2419 02f6 a40f and a,#15
2420 02f8 6b01 ld (OFST+0,sp),a
2421 ; 790 if (temp < 8)
2423 02fa a108 cp a,#8
2424 02fc 2414 jruge L1611
2425 ; 792 ADC1->AWSRL &= (u8)(~((u8)1 << temp));
2427 02fe 5f clrw x
2428 02ff 97 ld xl,a
2429 0300 a601 ld a,#1
2430 0302 5d tnzw x
2431 0303 2704 jreq L241
2432 0305 L441:
2433 0305 48 sll a
2434 0306 5a decw x
2435 0307 26fc jrne L441
2436 0309 L241:
2437 0309 43 cpl a
2438 030a c4540d and a,21517
2439 030d c7540d ld 21517,a
2441 0310 201f jra L5511
2442 0312 L1611:
2443 ; 796 ADC1->AWSRH &= (u8)(~((u8)1 << (temp - 8)));
2445 0312 a008 sub a,#8
2446 0314 5f clrw x
2447 0315 97 ld xl,a
2448 0316 a601 ld a,#1
2449 0318 5d tnzw x
2450 0319 2704 jreq L641
2451 031b L051:
2452 031b 48 sll a
2453 031c 5a decw x
2454 031d 26fc jrne L051
2455 031f L641:
2456 031f 43 cpl a
2457 0320 c4540c and a,21516
2458 0323 c7540c ld 21516,a
2459 0326 2009 jra L5511
2460 0328 L7511:
2461 ; 801 ADC1->CSR &= (u8) (~Flag);
2463 0328 7b02 ld a,(OFST+1,sp)
2464 032a 43 cpl a
2465 032b c45400 and a,21504
2466 032e c75400 ld 21504,a
2467 0331 L5511:
2468 ; 803 }
2471 0331 85 popw x
2472 0332 81 ret
2527 ; 833 ITStatus ADC1_GetITStatus(ADC1_IT_TypeDef ITPendingBit)
2527 ; 834 {
2528 switch .text
2529 0333 _ADC1_GetITStatus:
2531 0333 89 pushw x
2532 0334 88 push a
2533 00000001 OFST: set 1
2536 ; 835 ITStatus itstatus = RESET;
2538 ; 836 u8 temp = 0;
2540 ; 839 assert_param(IS_ADC1_ITPENDINGBIT_OK(ITPendingBit));
2542 ; 841 if ((ITPendingBit & 0xF0) == 0x10)
2544 0335 7b03 ld a,(OFST+2,sp)
2545 0337 a4f0 and a,#240
2546 0339 5f clrw x
2547 033a 02 rlwa x,a
2548 033b a30010 cpw x,#16
2549 033e 262c jrne L5121
2550 ; 844 temp = (u8)(ITPendingBit & 0x0F);
2552 0340 7b03 ld a,(OFST+2,sp)
2553 0342 a40f and a,#15
2554 0344 6b01 ld (OFST+0,sp),a
2555 ; 845 if (temp < 8)
2557 0346 a108 cp a,#8
2558 0348 2410 jruge L7121
2559 ; 847 itstatus = (u8)(ADC1->AWSRL & (u8)((u8)1 << temp));
2561 034a 5f clrw x
2562 034b 97 ld xl,a
2563 034c a601 ld a,#1
2564 034e 5d tnzw x
2565 034f 2704 jreq L451
2566 0351 L651:
2567 0351 48 sll a
2568 0352 5a decw x
2569 0353 26fc jrne L651
2570 0355 L451:
2571 0355 c4540d and a,21517
2573 0358 2017 jra L3221
2574 035a L7121:
2575 ; 851 itstatus = (u8)(ADC1->AWSRH & (u8)((u8)1 << (temp - 8)));
2577 035a a008 sub a,#8
2578 035c 5f clrw x
2579 035d 97 ld xl,a
2580 035e a601 ld a,#1
2581 0360 5d tnzw x
2582 0361 2704 jreq L061
2583 0363 L261:
2584 0363 48 sll a
2585 0364 5a decw x
2586 0365 26fc jrne L261
2587 0367 L061:
2588 0367 c4540c and a,21516
2589 036a 2005 jra L3221
2590 036c L5121:
2591 ; 856 itstatus = (u8)(ADC1->CSR & ITPendingBit);
2593 036c c65400 ld a,21504
2594 036f 1403 and a,(OFST+2,sp)
2595 0371 L3221:
2596 ; 858 return ((ITStatus)itstatus);
2600 0371 5b03 addw sp,#3
2601 0373 81 ret
2646 ; 889 void ADC1_ClearITPendingBit(ADC1_IT_TypeDef ITPendingBit)
2646 ; 890 {
2647 switch .text
2648 0374 _ADC1_ClearITPendingBit:
2650 0374 89 pushw x
2651 0375 88 push a
2652 00000001 OFST: set 1
2655 ; 891 u8 temp = 0;
2657 0376 0f01 clr (OFST+0,sp)
2658 ; 894 assert_param(IS_ADC1_ITPENDINGBIT_OK(ITPendingBit));
2660 ; 896 if ((ITPendingBit& 0xF0) == 0x10)
2662 0378 01 rrwa x,a
2663 0379 a4f0 and a,#240
2664 037b 5f clrw x
2665 037c 02 rlwa x,a
2666 037d a30010 cpw x,#16
2667 0380 2634 jrne L7421
2668 ; 899 temp = (u8)(ITPendingBit & 0x0F);
2670 0382 7b03 ld a,(OFST+2,sp)
2671 0384 a40f and a,#15
2672 0386 6b01 ld (OFST+0,sp),a
2673 ; 900 if (temp < 8)
2675 0388 a108 cp a,#8
2676 038a 2414 jruge L1521
2677 ; 902 ADC1->AWSRL &= (u8)(~((u8)1 << temp));
2679 038c 5f clrw x
2680 038d 97 ld xl,a
2681 038e a601 ld a,#1
2682 0390 5d tnzw x
2683 0391 2704 jreq L661
2684 0393 L071:
2685 0393 48 sll a
2686 0394 5a decw x
2687 0395 26fc jrne L071
2688 0397 L661:
2689 0397 43 cpl a
2690 0398 c4540d and a,21517
2691 039b c7540d ld 21517,a
2693 039e 201f jra L5521
2694 03a0 L1521:
2695 ; 906 ADC1->AWSRH &= (u8)(~((u8)1 << (temp - 8)));
2697 03a0 a008 sub a,#8
2698 03a2 5f clrw x
2699 03a3 97 ld xl,a
2700 03a4 a601 ld a,#1
2701 03a6 5d tnzw x
2702 03a7 2704 jreq L271
2703 03a9 L471:
2704 03a9 48 sll a
2705 03aa 5a decw x
2706 03ab 26fc jrne L471
2707 03ad L271:
2708 03ad 43 cpl a
2709 03ae c4540c and a,21516
2710 03b1 c7540c ld 21516,a
2711 03b4 2009 jra L5521
2712 03b6 L7421:
2713 ; 911 ADC1->CSR &= (u8) (~ITPendingBit);
2715 03b6 7b03 ld a,(OFST+2,sp)
2716 03b8 43 cpl a
2717 03b9 c45400 and a,21504
2718 03bc c75400 ld 21504,a
2719 03bf L5521:
2720 ; 913 }
2723 03bf 5b03 addw sp,#3
2724 03c1 81 ret
2737 xdef _ADC1_ClearITPendingBit
2738 xdef _ADC1_GetITStatus
2739 xdef _ADC1_ClearFlag
2740 xdef _ADC1_GetFlagStatus
2741 xdef _ADC1_GetAWDChannelStatus
2742 xdef _ADC1_GetBufferValue
2743 xdef _ADC1_SetLowThreshold
2744 xdef _ADC1_SetHighThreshold
2745 xdef _ADC1_GetConversionValue
2746 xdef _ADC1_StartConversion
2747 xdef _ADC1_AWDChannelConfig
2748 xdef _ADC1_ExternalTriggerConfig
2749 xdef _ADC1_ConversionConfig
2750 xdef _ADC1_SchmittTriggerConfig
2751 xdef _ADC1_PrescalerConfig
2752 xdef _ADC1_ITConfig
2753 xdef _ADC1_DataBufferCmd
2754 xdef _ADC1_ScanModeCmd
2755 xdef _ADC1_Cmd
2756 xdef _ADC1_Init
2757 xdef _ADC1_DeInit
2776 end
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