📄 stm8s_adc1.ls
字号:
1364 0145 c65400 ld a,21504
1365 0148 1a02 or a,(OFST+2,sp)
1366 014a c75400 ld 21504,a
1367 ; 422 }
1370 014d 85 popw x
1371 014e 81 ret
1417 ; 444 void ADC1_ExternalTriggerConfig(ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState ADC1_ExtTrigState)
1417 ; 445 {
1418 switch .text
1419 014f _ADC1_ExternalTriggerConfig:
1421 014f 89 pushw x
1422 00000000 OFST: set 0
1425 ; 448 assert_param(IS_ADC1_EXTTRIG_OK(ADC1_ExtTrigger));
1427 ; 449 assert_param(IS_FUNCTIONALSTATE_OK(ADC1_ExtTrigState));
1429 ; 452 ADC1->CR2 &= (u8)(~ADC1_CR2_EXTSEL);
1431 0150 c65402 ld a,21506
1432 0153 a4cf and a,#207
1433 0155 c75402 ld 21506,a
1434 ; 454 if (ADC1_ExtTrigState != DISABLE)
1436 0158 9f ld a,xl
1437 0159 4d tnz a
1438 015a 2706 jreq L506
1439 ; 457 ADC1->CR2 |= (u8)(ADC1_CR2_EXTTRIG);
1441 015c 721c5402 bset 21506,#6
1443 0160 2004 jra L706
1444 0162 L506:
1445 ; 462 ADC1->CR2 &= (u8)(~ADC1_CR2_EXTTRIG);
1447 0162 721d5402 bres 21506,#6
1448 0166 L706:
1449 ; 466 ADC1->CR2 |= (u8)(ADC1_ExtTrigger);
1451 0166 c65402 ld a,21506
1452 0169 1a01 or a,(OFST+1,sp)
1453 016b c75402 ld 21506,a
1454 ; 468 }
1457 016e 85 popw x
1458 016f 81 ret
1482 ; 488 void ADC1_StartConversion(void)
1482 ; 489 {
1483 switch .text
1484 0170 _ADC1_StartConversion:
1488 ; 490 ADC1->CR1 |= ADC1_CR1_ADON;
1490 0170 72105401 bset 21505,#0
1491 ; 491 }
1494 0174 81 ret
1538 ; 509 u16 ADC1_GetConversionValue(void)
1538 ; 510 {
1539 switch .text
1540 0175 _ADC1_GetConversionValue:
1542 0175 5205 subw sp,#5
1543 00000005 OFST: set 5
1546 ; 512 u16 temph = 0;
1548 ; 513 u8 templ = 0;
1550 ; 515 if (ADC1->CR2 & ADC1_CR2_ALIGN) /* Right alignment */
1552 0177 720754020e btjf 21506,#3,L346
1553 ; 518 templ = ADC1->DRL;
1555 017c c65405 ld a,21509
1556 017f 6b03 ld (OFST-2,sp),a
1557 ; 520 temph = ADC1->DRH;
1559 0181 c65404 ld a,21508
1560 0184 97 ld xl,a
1561 ; 522 temph = (u16)(templ | (u16)(temph << (u8)8));
1563 0185 7b03 ld a,(OFST-2,sp)
1564 0187 02 rlwa x,a
1566 0188 201a jra L546
1567 018a L346:
1568 ; 527 temph = ADC1->DRH;
1570 018a c65404 ld a,21508
1571 018d 97 ld xl,a
1572 ; 529 templ = ADC1->DRL;
1574 018e c65405 ld a,21509
1575 0191 6b03 ld (OFST-2,sp),a
1576 ; 531 temph = (u16)((u16)(templ << (u8)6) | (u16)(temph << (u8)8));
1578 0193 4f clr a
1579 0194 02 rlwa x,a
1580 0195 1f01 ldw (OFST-4,sp),x
1581 0197 7b03 ld a,(OFST-2,sp)
1582 0199 97 ld xl,a
1583 019a a640 ld a,#64
1584 019c 42 mul x,a
1585 019d 01 rrwa x,a
1586 019e 1a02 or a,(OFST-3,sp)
1587 01a0 01 rrwa x,a
1588 01a1 1a01 or a,(OFST-4,sp)
1589 01a3 01 rrwa x,a
1590 01a4 L546:
1591 ; 534 return ((u16)temph);
1595 01a4 5b05 addw sp,#5
1596 01a6 81 ret
1642 ; 555 void ADC1_AWDChannelConfig(ADC1_Channel_TypeDef Channel, FunctionalState NewState)
1642 ; 556 {
1643 switch .text
1644 01a7 _ADC1_AWDChannelConfig:
1646 01a7 89 pushw x
1647 00000000 OFST: set 0
1650 ; 558 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1652 ; 559 assert_param(IS_ADC1_CHANNEL_OK(Channel));
1654 ; 561 if (Channel < (u8)8)
1656 01a8 9e ld a,xh
1657 01a9 a108 cp a,#8
1658 01ab 242b jruge L176
1659 ; 563 if (NewState != DISABLE)
1661 01ad 9f ld a,xl
1662 01ae 4d tnz a
1663 01af 2711 jreq L376
1664 ; 565 ADC1->AWCRL |= (u8)((u8)1 << Channel);
1666 01b1 9e ld a,xh
1667 01b2 5f clrw x
1668 01b3 97 ld xl,a
1669 01b4 a601 ld a,#1
1670 01b6 5d tnzw x
1671 01b7 2704 jreq L66
1672 01b9 L07:
1673 01b9 48 sll a
1674 01ba 5a decw x
1675 01bb 26fc jrne L07
1676 01bd L66:
1677 01bd ca540f or a,21519
1679 01c0 2011 jp LC004
1680 01c2 L376:
1681 ; 569 ADC1->AWCRL &= (u8)(~((u8)1 << Channel));
1683 01c2 7b01 ld a,(OFST+1,sp)
1684 01c4 5f clrw x
1685 01c5 97 ld xl,a
1686 01c6 a601 ld a,#1
1687 01c8 5d tnzw x
1688 01c9 2704 jreq L27
1689 01cb L47:
1690 01cb 48 sll a
1691 01cc 5a decw x
1692 01cd 26fc jrne L47
1693 01cf L27:
1694 01cf 43 cpl a
1695 01d0 c4540f and a,21519
1696 01d3 LC004:
1697 01d3 c7540f ld 21519,a
1698 01d6 202e jra L776
1699 01d8 L176:
1700 ; 574 if (NewState != DISABLE)
1702 01d8 7b02 ld a,(OFST+2,sp)
1703 01da 2714 jreq L107
1704 ; 576 ADC1->AWCRH |= (u8)((u8)1 << (Channel - (u8)8));
1706 01dc 7b01 ld a,(OFST+1,sp)
1707 01de a008 sub a,#8
1708 01e0 5f clrw x
1709 01e1 97 ld xl,a
1710 01e2 a601 ld a,#1
1711 01e4 5d tnzw x
1712 01e5 2704 jreq L67
1713 01e7 L001:
1714 01e7 48 sll a
1715 01e8 5a decw x
1716 01e9 26fc jrne L001
1717 01eb L67:
1718 01eb ca540e or a,21518
1720 01ee 2013 jp LC003
1721 01f0 L107:
1722 ; 580 ADC1->AWCRH &= (u8)(~((u8)1 << (Channel - (u8)8)));
1724 01f0 7b01 ld a,(OFST+1,sp)
1725 01f2 a008 sub a,#8
1726 01f4 5f clrw x
1727 01f5 97 ld xl,a
1728 01f6 a601 ld a,#1
1729 01f8 5d tnzw x
1730 01f9 2704 jreq L201
1731 01fb L401:
1732 01fb 48 sll a
1733 01fc 5a decw x
1734 01fd 26fc jrne L401
1735 01ff L201:
1736 01ff 43 cpl a
1737 0200 c4540e and a,21518
1738 0203 LC003:
1739 0203 c7540e ld 21518,a
1740 0206 L776:
1741 ; 583 }
1744 0206 85 popw x
1745 0207 81 ret
1780 ; 600 void ADC1_SetHighThreshold(u16 Threshold)
1780 ; 601 {
1781 switch .text
1782 0208 _ADC1_SetHighThreshold:
1784 0208 89 pushw x
1785 00000000 OFST: set 0
1788 ; 602 ADC1->HTRH = (u8)(Threshold >> (u8)2);
1790 0209 54 srlw x
1791 020a 54 srlw x
1792 020b 9f ld a,xl
1793 020c c75408 ld 21512,a
1794 ; 603 ADC1->HTRL = (u8)Threshold;
1796 020f 7b02 ld a,(OFST+2,sp)
1797 0211 c75409 ld 21513,a
1798 ; 604 }
1801 0214 85 popw x
1802 0215 81 ret
1837 ; 621 void ADC1_SetLowThreshold(u16 Threshold)
1837 ; 622 {
1838 switch .text
1839 0216 _ADC1_SetLowThreshold:
1841 0216 89 pushw x
1842 00000000 OFST: set 0
1845 ; 623 ADC1->LTRH = (u8)(Threshold >> (u8)2);
1847 0217 54 srlw x
1848 0218 54 srlw x
1849 0219 9f ld a,xl
1850 021a c7540a ld 21514,a
1851 ; 624 ADC1->LTRL = (u8)Threshold;
1853 021d 7b02 ld a,(OFST+2,sp)
1854 021f c7540b ld 21515,a
1855 ; 625 }
1858 0222 85 popw x
1859 0223 81 ret
1912 ; 642 u16 ADC1_GetBufferValue(u8 Buffer)
1912 ; 643 {
1913 switch .text
1914 0224 _ADC1_GetBufferValue:
1916 0224 88 push a
1917 0225 5205 subw sp,#5
1918 00000005 OFST: set 5
1921 ; 645 u16 temph = 0;
1923 ; 646 u8 templ = 0;
1925 ; 649 assert_param(IS_ADC1_BUFFER_OK(Buffer));
1927 ; 651 if (ADC1->CR2 & ADC1_CR2_ALIGN) /* Right alignment */
1929 0227 7b06 ld a,(OFST+1,sp)
1930 0229 5f clrw x
1931 022a 97 ld xl,a
1932 022b 58 sllw x
1933 022c 720754020e btjf 21506,#3,L767
1934 ; 654 templ = *(u8*)(ADC1_BaseAddress + (Buffer << 1) + 1);
1936 0231 d653e1 ld a,(21473,x)
1937 0234 6b03 ld (OFST-2,sp),a
1938 ; 656 temph = *(u8*)(ADC1_BaseAddress + (Buffer << 1));
1940 0236 d653e0 ld a,(21472,x)
1941 0239 97 ld xl,a
1942 ; 658 temph = (u16)(templ | (u16)(temph << (u8)8));
1944 023a 7b03 ld a,(OFST-2,sp)
1945 023c 02 rlwa x,a
1947 023d 2024 jra L177
1948 023f L767:
1949 ; 663 temph = *(u8*)(ADC1_BaseAddress + (Buffer << 1));
1951 023f d653e0 ld a,(21472,x)
1952 0242 5f clrw x
1953 0243 97 ld xl,a
1954 0244 1f04 ldw (OFST-1,sp),x
1955 ; 665 templ = *(u8*)(ADC1_BaseAddress + (Buffer << 1) + 1);
1957 0246 5f clrw x
1958 0247 7b06 ld a,(OFST+1,sp)
1959 0249 97 ld xl,a
1960 024a 58 sllw x
1961 024b d653e1 ld a,(21473,x)
1962 024e 6b03 ld (OFST-2,sp),a
1963 ; 667 temph = (u16)((u16)(templ << (u8)6) | (u16)(temph << (u8)8));
1965 0250 4f clr a
1966 0251 1e04 ldw x,(OFST-1,sp)
1967 0253 02 rlwa x,a
1968 0254 1f01 ldw (OFST-4,sp),x
1969 0256 7b03 ld a,(OFST-2,sp)
1970 0258 97 ld xl,a
1971 0259 a640 ld a,#64
1972 025b 42 mul x,a
1973 025c 01 rrwa x,a
1974 025d 1a02 or a,(OFST-3,sp)
1975 025f 01 rrwa x,a
1976 0260 1a01 or a,(OFST-4,sp)
1977 0262 01 rrwa x,a
1978 0263 L177:
1979 ; 670 return ((u16)temph);
1983 0263 5b06 addw sp,#6
1984 0265 81 ret
2050 ; 690 FlagStatus ADC1_GetAWDChannelStatus(ADC1_Channel_TypeDef Channel)
2050 ; 691 {
2051 switch .text
2052 0266 _ADC1_GetAWDChannelStatus:
2054 0266 88 push a
2055 0267 88 push a
2056 00000001 OFST: set 1
2059 ; 692 u8 status = 0;
2061 0268 0f01 clr (OFST+0,sp)
2062 ; 695 assert_param(IS_ADC1_CHANNEL_OK(Channel));
2064 ; 697 if (Channel < (u8)8)
2066 026a a108 cp a,#8
2067 026c 2410 jruge L5201
2068 ; 699 status = (u8)(ADC1->AWSRL & ((u8)1 << Channel));
2070 026e 5f clrw x
2071 026f 97 ld xl,a
2072 0270 a601 ld a,#1
2073 0272 5d tnzw x
2074 0273 2704 jreq L611
2075 0275 L021:
2076 0275 48 sll a
2077 0276 5a decw x
2078 0277 26fc jrne L021
2079 0279 L611:
2080 0279 c4540d and a,21517
2082 027c 2012 jra L7201
2083 027e L5201:
2084 ; 703 status = (u8)(ADC1->AWSRH & ((u8)1 << (Channel - (u8)8)));
2086 027e 7b02 ld a,(OFST+1,sp)
2087 0280 a008 sub a,#8
2088 0282 5f clrw x
2089 0283 97 ld xl,a
2090 0284 a601 ld a,#1
2091 0286 5d tnzw x
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