📄 dbgserial.c
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//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
// File: dbgserial.c
//
// This module is provides the interface to the serial port.
//
#include <xllp_defs.h>
#include <mainstoneii.h>
#include <bulverde_uart.h>
#include <bulverde_gpio.h>
#include <bulverde_clkmgr.h>
#include <bulverde_base_regs.h>
//------------------------------------------------------------------------------
// Defines
//
#define UINT8 unsigned char
#define UINT32 unsigned long
#define FALSE 0
#define false 0
#define TRUE 1
#define true 1
#define DEBUG_BAUD_38400 0x00000018
void OEMWriteDebugByte(UINT8 ch);
void OEMWriteDebugString(unsigned char * string);
//------------------------------------------------------------------------------
// Externs
//
//------------------------------------------------------------------------------
// Global Variables
//------------------------------------------------------------------------------
// Local Variables
//
static volatile BULVERDE_UART_REG *g_pDebugUARTPort = NULL;
//static volatile MAINSTONEII_BLR_REGS *g_pBLRegs = NULL;
//------------------------------------------------------------------------------
// Local Functions
//
//------------------------------------------------------------------------------
//
// Function: OEMInitDebugSerial
//
// Initializes the debug serial port
//
void InitDebugSerial(UINT32 DbgSerPhysAddr)
{
// UINT32 logMask = 0;
volatile BULVERDE_GPIO_REG *pGPIO_REGS = NULL;
volatile BULVERDE_CLKMGR_REG *pCLKMGR_REGS = NULL;
// At this moment we must suppress logging.
//
// logMask = g_oalLogMask;
// g_oalLogMask = 0;
g_pDebugUARTPort = (volatile BULVERDE_UART_REG *) DbgSerPhysAddr;
pGPIO_REGS = (volatile BULVERDE_GPIO_REG *) BULVERDE_BASE_REG_PA_GPIO;
pCLKMGR_REGS = (volatile BULVERDE_CLKMGR_REG *) BULVERDE_BASE_REG_PA_CLKMGR;
// Map the Mainstone board-level registers which are used in the OEMWriteDebugLED routine.
//
// g_pBLRegs = (volatile MAINSTONEII_BLR_REGS *) OALPAtoVA(MAINSTONEII_BASE_REG_PA_FPGA, FALSE);
// Ensure that UART interrupts are turned off.
//
g_pDebugUARTPort->lcr = 0x0; // Clear DLAB.
g_pDebugUARTPort->ier_dlh = 0x0; // IER_DLH = 0x0.
// Set the Baud Rate (Divisor low = DEBUG_BAUD_38400).
// The divisor latches are at offsets 0 and 1, which are
// receive/transmit data and ier registers.
//
g_pDebugUARTPort->lcr = 0x80; // Access Divisor.
g_pDebugUARTPort->thr_rbr_dll = DEBUG_BAUD_38400; // Low byte divisor.
g_pDebugUARTPort->ier_dlh = 0x00; // High byte divisor.
g_pDebugUARTPort->lcr = 0x0; // Clear DLAB.
//Setting UART properties to 8N1
//
g_pDebugUARTPort->lcr = 0x3; // 8 bits, 1 stop, no parity. Also LCR DLAB bit = 0.
g_pDebugUARTPort->iir_fcr = 0x01; // Enable the FIFO.
g_pDebugUARTPort->iir_fcr = 0x07; // Clear Rx,Tx FIFOs.
// Don't enable UART interrupts - we'll poll for the data.
//
g_pDebugUARTPort->ier_dlh = 0x0;
// Ensure loop-back test mode is off even though MCR reset value is 0x0.
//
g_pDebugUARTPort->mcr = 0x0; // UART is in normal mode.
// Configure GPIO pins for FFUART
//
if (DbgSerPhysAddr == BULVERDE_BASE_REG_PA_FFUART)
{
// Initialize GPIO pins.
// Write 0 on GPIO pins 39, 40 and 41 before configuring them as outputs.
//
pGPIO_REGS->GPCR1 = ( XLLP_GPIO_BIT_FFDTR | XLLP_GPIO_BIT_FFTXD |
XLLP_GPIO_BIT_FFRTS );
// Configure direction of GPIO pins 34, 35, 36, 37 and 38 as input
// and GPIO pins 39, 40 and 41 as output
//
pGPIO_REGS->GPDR1 &= ~( XLLP_GPIO_BIT_FFRXD | XLLP_GPIO_BIT_FFCTS |
XLLP_GPIO_BIT_FFDCD | XLLP_GPIO_BIT_FFDSR |
XLLP_GPIO_BIT_FFRI );
pGPIO_REGS->GPDR1 |= ( XLLP_GPIO_BIT_FFTXD | XLLP_GPIO_BIT_FFDTR |
XLLP_GPIO_BIT_FFRTS );
// Configure GPIO pins 34, 35, 36, 37 and 38 for Alt_fn1. And pins 39, 40 and 41 for Alt_fn2.
//
pGPIO_REGS->GAFR1_L |= ( XLLP_GPIO_AF_BIT_FFRXD | XLLP_GPIO_AF_BIT_FFCTS |
XLLP_GPIO_AF_BIT_FFDCD | XLLP_GPIO_AF_BIT_FFDSR |
XLLP_GPIO_AF_BIT_FFRI | XLLP_GPIO_AF_BIT_FFTXD |
XLLP_GPIO_AF_BIT_FFDTR | XLLP_GPIO_AF_BIT_FFRTS );
// Enable the FFUART clock.
//
pCLKMGR_REGS->cken |= XLLP_CLKEN_FFUART ;
}
else if (DbgSerPhysAddr == BULVERDE_BASE_REG_PA_BTUART)
{
// Initialize GPIO pins.
// Write 0 on GPIO pins 43 and 45 before configuring them as outputs.
//
pGPIO_REGS->GPCR1 = (XLLP_GPIO_BIT_BTTXD | XLLP_GPIO_BIT_BTRTS);
// Configure direction of GPIO pins 42 and 44 as input
// and GPIO pins 43 and 45 as output.
//
pGPIO_REGS->GPDR1 &= ~( XLLP_GPIO_BIT_BTRXD | XLLP_GPIO_BIT_BTCTS);
pGPIO_REGS->GPDR1 |= ( XLLP_GPIO_BIT_BTTXD | XLLP_GPIO_BIT_BTRTS);
// Configure GPIO pins 42 and 44 for Alt_fn1. And pins 43 and 45 for Alt_fn2.
//
pGPIO_REGS->GAFR1_L |= ( XLLP_GPIO_AF_BIT_BTRXD | XLLP_GPIO_AF_BIT_BTCTS |
XLLP_GPIO_AF_BIT_BTTXD | XLLP_GPIO_AF_BIT_BTRTS );
// Turn on the BTUART transceiver.
//
// g_pBLRegs->misc_wr |= nBT_OFF_MASK;
// Enable the BTUART clock.
//
pCLKMGR_REGS->cken |= XLLP_CLKEN_BTUART ;
}
// Enable the UART.
//
g_pDebugUARTPort->ier_dlh = 0x40;
// Restore the logging mask.
//
// g_oalLogMask = logMask;
}
//------------------------------------------------------------------------------
//
// Function: OEMWriteDebugByte
//
// Transmits a character out the debug serial port.
//
void OEMWriteDebugByte(UINT8 ch)
{
if (!g_pDebugUARTPort)
{
return;
}
// Spin if FIFO has more than half data.
//
while(!(g_pDebugUARTPort->lsr & 0x020));
// Write a character byte to the FIFO.
//
g_pDebugUARTPort->thr_rbr_dll = (unsigned char)ch;
}
//------------------------------------------------------------------------------
//
// Function: OEMReadDebugByte
//
// Reads a byte from the debug serial port. Does not wait for a character.
// If a character is not available function returns "OEM_DEBUG_READ_NODATA".
//
int OEMReadDebugByte()
{
UINT32 data = -1;
UINT32 LSR;
if (!g_pDebugUARTPort)
{
return(data);
}
// Read LSR.
//
LSR = g_pDebugUARTPort->lsr;
// Return if no data.
//
if(!(LSR & 0x1))
{
return(data);
}
// Read data.
//
data = g_pDebugUARTPort->thr_rbr_dll;
// Signal error if PE or FE was set.
// Do nothing if BI or OE was set.
//
if(LSR & 0x0c)
{
data = -1;
}
return(data);
}
//------------------------------------------------------------------------------
//
// Function: OEMClearDebugCommError
//
// Clears communications errors (flushes the serial FIFO).
//
void OEMClearDebugCommError(void)
{
while(OEMReadDebugByte() == -1);
}
//----------------------------
//
// Function: OEMWriteDebugByte
void OEMWriteDebugString(unsigned char * string)
{
while(*string!='\0')
OEMWriteDebugByte((UINT8)*string++);
}
//-----------------------------------------------------------------------------
//---------------------------------------------------------------------------
//Function: uart_init
//
void uart_test(unsigned char com)
{
unsigned char str[]="UART initailized done\r\n";
switch(com)
{
case FFUART:
InitDebugSerial(BULVERDE_BASE_REG_PA_FFUART);
break;
case BTUART:
InitDebugSerial(BULVERDE_BASE_REG_PA_BTUART);
break;
case STUART:
InitDebugSerial(BULVERDE_BASE_REG_PA_STUART);
break;
default:
break;
}
//while(1)
//{
OEMWriteDebugString(str);
//}
}
void Test_SDRAM()
{
UINT32 i;
UINT32 start = 0xA0000000;
UINT32 end = 0xA2000000;
unsigned char buffer[]="FFFFFFFF";
unsigned char str[]="Data of the address FFFFFFFF is ";
for(i = start; i<end; i+=4)
{
*((volatile UINT32* )i) = i;
if(*((volatile UINT32* )i) == i)
{
sprintf(str, "Data of the address %X is ",i);
OEMWriteDebugString(str);
sprintf(buffer, "%X",*((volatile UINT32* )i));
OEMWriteDebugString(buffer);
OEMWriteDebugByte('\r');
OEMWriteDebugByte('\n');
}
}
}
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