xsbase270_g.h

PXA27X裸机测试程序

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
//  File: XSBASE270_G.h
//
//  This header file contains XSBASE270_G specific definitions.
//
#ifndef __XSBASE270_G_H__
#define __XSBASE270_G_H__

//#define UINT unsigned long;
#define UINT32 unsigned long
//UINT xlli_power_off(VOID);

//
// XSBASE270_G: (on PDC): nCS0: Boot FLASH (32MB)
//
#define XSBASE270_G_BASE_PA_BOOT_FLASH           0x00000000
#define XSBASE270_G_SIZE_BOOT_FLASH              0x04000000

//
// XSBASE270_G: nCS2: Board-Control Registers (CPLD)
//
#define XSBASE270_G_BASE_REG_PA_CPLD             0x0A000000

//
// XSBASE270_G: nCS3: Ethernet (SMSC 91C111)
//
#define XSBASE270_G_BASE_REG_PA_SMSC_ETHERNET    0x0C000000

//
// XSBASE270_G: nCS4: USB2.0 Controller
//
#define XSBASE270_G_BASE_REG_PA_USB_CONT         0x10000000

//
// XSBASE270_G: nCS5: eXpansion Board Header
//
#define XSBASE270_G_BASE_PA_XDC                  0x14000000

//
// XSBASE270_G: nSDCS0: SDRAM(64MB)
//
#define XSBASE270_G_BASE_PA_SDRAM                0xA0000000
#define XSBASE270_G_SIZE_SDRAM                   0x04000000

//
//  XSBASE270_G: CPLD Registers
//
typedef struct
{
    UINT32    BCR1;        // 0A00_0000
    UINT32    BCR2;        // 0A00_0004
    UINT32    STATUS;      // 0A00_0008
    UINT32    SWITCH;      // 0A00_000C
    UINT32    INT;         // 0A00_0010
} XSBASE270_G_CPLD_REGS, *PXSBASE270_G_CPLD_REGS;

// <BELOW ITEMS UNTOUCHED FROM COTULLA>

//
// Processor Stepping Values
//

#define BULVERDE_CP15_A0_VAL 0x69054110
#define BULVERDE_CP15_A1_VAL 0x69054111
#define BULVERDE_CP15_B0_VAL 0x69054112

#define BULVERDE_JTAG_A0_VAL 0x09265013
#define BULVERDE_JTAG_A1_VAL 0x19265013
#define BULVERDE_JTAG_B0_VAL 0x29265013

#define BCR_CF_POWER  	0x00000001
#define BCR_CF_RESET  	0x00000002
#define BCR_IRDA_FSEL 	0x00000004
#define BCR_IRDA_MD0  	0x00000008
#define BCR_IRDA_MD1  	0x00000010
#define BCR_CF_BUS    	0x00000020
#define BCR_AUDIO     	0x00000040
#define BCR_LCD_PWR 	0x00000100
#define BCR_RED_LED 	0x00001000
#define BCR_GREEN_LED 	0x00002000
#define BCR_SPRK    	0x00004000
#define BCR_MMC_PWR   	0x00008000

#define BCR2_MS_PWR  	0x00000001
#define BCR2_VBUS_ON  	0x00000002
#define BCR2_I2C_EN  	0x00000004
#define BCR2_DAC_ON  	0x00000008
#define BCR2_MBREQ_EN 	0x00000010
#define BCR2_FLY_EN  	0x00000020

#define STS_CF_DET    	0x00000001
#define STS_BVD1      	0x00000002
#define STS_BVD2      	0x00000004
#define STS_MMC_DET   	0x00000008
#define STS_MMC_WP    	0x00000010
#define STS_SIM_DET   	0x00000020
#define STS_MS_DET    	0x00000040
#define STS_POLL_FLAG 	0x00000080
#define STS_USB1_WAKE 	0x00000100
#define STS_DIP_FLASH 	0x00000200
#define STS_EX_PRES   	0x00000400
#define STS_EX_IN0    	0x00000800
#define STS_EX_IN1    	0x00001000

#define INT_MMC_IN 		0x00000001
#define INT_MMC_OUT 	0x00000002
#define INT_SIM_IN 		0x00000004
#define INT_SIM_OUT 	0x00000008
#define INT_USB_IN 		0x00000010
#define INT_USB_OUT 	0x00000020
#define INT_CF_IN 		0x00000040
#define INT_CF_OUT 		0x00000080
#define INT_SW1 		0x00000100
#define INT_SW2	 		0x00000200
#define INT_SW3	 		0x00000400
#define INT_SW4_1	 	0x00000800
#define INT_SW4_2	 	0x00001000
#define INT_SW4_3		0x00002000

#endif    // __XSBASE270_G_H__.