xllp_gpio.h

PXA27X裸机测试程序

/* Pin  56  alternate functions */
#define XLLP_GPIO_AF_PCMCIA_nPWAIT		XLLP_GPIO_ALT_FN_1
#define XLLP_GPIO_AF_BB_IB_DAT2			XLLP_GPIO_ALT_FN_2

/* Pin  57  alternate functions */
#define XLLP_GPIO_AF_PCMCIA_nIOIS16		XLLP_GPIO_ALT_FN_1
#define XLLP_GPIO_AF_BB_IB_DAT3			XLLP_GPIO_ALT_FN_2

/* Pin  58  alternate functions */
#define XLLP_GPIO_AF_L_DD0				XLLP_GPIO_ALT_FN_2

/* Pin  59  alternate functions */
#define XLLP_GPIO_AF_L_DD1				XLLP_GPIO_ALT_FN_2

/* Pin  60  alternate functions */
#define XLLP_GPIO_AF_L_DD2				XLLP_GPIO_ALT_FN_2

/* Pin  61  alternate functions */
#define XLLP_GPIO_AF_L_DD3				XLLP_GPIO_ALT_FN_2

/* Pin  62  alternate functions */
#define XLLP_GPIO_AF_L_DD4				XLLP_GPIO_ALT_FN_2

/* Pin  63  alternate functions */
#define XLLP_GPIO_AF_L_DD5				XLLP_GPIO_ALT_FN_2

/* Pin  64  alternate functions */
#define XLLP_GPIO_AF_L_DD6				XLLP_GPIO_ALT_FN_2

/* Pin  65  alternate functions */
#define XLLP_GPIO_AF_L_DD7				XLLP_GPIO_ALT_FN_2

/* Pin  66  alternate functions */
#define XLLP_GPIO_AF_L_DD8				XLLP_GPIO_ALT_FN_2

/* Pin  67  alternate functions */
#define XLLP_GPIO_AF_L_DD9				XLLP_GPIO_ALT_FN_2

/* Pin  68  alternate functions */
#define XLLP_GPIO_AF_L_DD10				XLLP_GPIO_ALT_FN_2

/* Pin  69  alternate functions */
#define XLLP_GPIO_AF_L_DD11				XLLP_GPIO_ALT_FN_2

/* Pin  70  alternate functions */
#define XLLP_GPIO_AF_L_DD12				XLLP_GPIO_ALT_FN_2

/* Pin  71  alternate functions */
#define XLLP_GPIO_AF_L_DD13				XLLP_GPIO_ALT_FN_2

/* Pin  72  alternate functions */
#define XLLP_GPIO_AF_L_DD14				XLLP_GPIO_ALT_FN_2

/* Pin  73  alternate functions */
#define XLLP_GPIO_AF_L_DD15				XLLP_GPIO_ALT_FN_2

/* Pin  74  alternate functions */
#define XLLP_GPIO_AF_L_FCLK_RD			XLLP_GPIO_ALT_FN_2

/* Pin  75  alternate functions */
#define XLLP_GPIO_AF_L_LCLK_A0			XLLP_GPIO_ALT_FN_2

/* Pin  76  alternate functions */
#define XLLP_GPIO_AF_L_PCLK_WR			XLLP_GPIO_ALT_FN_2

/* Pin  77  alternate functions */
#define XLLP_GPIO_AF_L_BIAS				XLLP_GPIO_ALT_FN_2

/* Pin  78  alternate functions */
#define XLLP_GPIO_AF_nCS2				XLLP_GPIO_ALT_FN_2

/* Pin  79  alternate functions */
#define XLLP_GPIO_AF_PCMCIA_PSKTSEL		XLLP_GPIO_ALT_FN_1

/* Pin  80  alternate functions */
#define XLLP_GPIO_AF_nCS4				XLLP_GPIO_ALT_FN_2

/* Pin  81  alternate functions */
#define XLLP_GPIO_AF_BB_OB_DAT0			XLLP_GPIO_ALT_FN_2

/* Pin  81  alternate functions */
#define XLLP_GPIO_AF_SSPTXD3			XLLP_GPIO_ALT_FN_1

/* Pin  82  alternate functions */
#define XLLP_GPIO_AF_BB_IB_DAT0			XLLP_GPIO_ALT_FN_2

/* Pin  82  alternate functions */
#define XLLP_GPIO_AF_SSPRXD3			XLLP_GPIO_ALT_FN_1

/* Pin  83  alternate functions */
#define XLLP_GPIO_AF_BB_IB_CLK			XLLP_GPIO_ALT_FN_2

/* Pin  83  alternate functions */
#define XLLP_GPIO_AF_SSPSFRM3			XLLP_GPIO_ALT_FN_1

/* Pin  84  alternate functions */
#define XLLP_GPIO_AF_BB_IB_STB			XLLP_GPIO_ALT_FN_2

/* Pin  85  alternate functions */
#define XLLP_GPIO_AF_PCMCIA_nPCE1		XLLP_GPIO_ALT_FN_1
#define XLLP_GPIO_AF_BB_IB_WAIT			XLLP_GPIO_ALT_FN_2

/* Pin  86  alternate functions */
#define XLLP_GPIO_AF_L_DD16				XLLP_GPIO_ALT_FN_2

/* Pin  86  alternate functions */
#define XLLP_GPIO_AF_PCMCIA_nPCE1_1		XLLP_GPIO_ALT_FN_1

/* Pin  87  alternate functions */
#define XLLP_GPIO_AF_L_DD17				XLLP_GPIO_ALT_FN_2

/* Pin  87  alternate functions */
#define XLLP_GPIO_AF_PCMCIA_nPCE1_2		XLLP_GPIO_ALT_FN_1

/* Pin  88  alternate functions */
#define XLLP_GPIO_AF_USBHPWR0			XLLP_GPIO_ALT_FN_1

/* Pin  88  alternate functions */
#define XLLP_GPIO_AF_SSPFRM2			XLLP_GPIO_ALT_FN_3

/* Pin  89  alternate functions */
#define XLLP_GPIO_AF_USBHPEN0			XLLP_GPIO_ALT_FN_2

/* Pin  90  alternate functions */
#define XLLP_GPIO_AF_URST				XLLP_GPIO_ALT_FN_2

/* Pin  90  alternate functions */
#define XLLP_GPIO_AF_CIF_DD4			XLLP_GPIO_ALT_FN_3

/* Pin  91  alternate functions */
#define XLLP_GPIO_AF_UCLK				XLLP_GPIO_ALT_FN_2

/* Pin  91  alternate functions */
#define XLLP_GPIO_AF_CIF_DD5			XLLP_GPIO_ALT_FN_3

/* Pin  92  alternate functions */
#define XLLP_GPIO_AF_MMDAT0				XLLP_GPIO_ALT_FN_1
#define XLLP_GPIO_AF_MSBS				XLLP_GPIO_ALT_FN_2

/* Pin  93  alternate functions */
#define XLLP_GPIO_AF_KP_DKIN0			XLLP_GPIO_ALT_FN_1

/* Pin  94  alternate functions */
#define XLLP_GPIO_AF_KP_DKIN1			XLLP_GPIO_ALT_FN_1

/* Pin  95  alternate functions */
#define XLLP_GPIO_AF_KP_MKIN6			XLLP_GPIO_ALT_FN_3

/* Pin  96  alternate functions */
#define XLLP_GPIO_AF_KP_MKOUT6			XLLP_GPIO_ALT_FN_3

/* Pin  97  alternate functions */
#define XLLP_GPIO_AF_KP_MKIN3			XLLP_GPIO_ALT_FN_3

/* Pin  98  alternate functions */
#define XLLP_GPIO_AF_KP_MKIN4			XLLP_GPIO_ALT_FN_3

/* Pin  99  alternate functions */
#define XLLP_GPIO_AF_KP_MKIN5			XLLP_GPIO_ALT_FN_3

/* Pin  100  alternate functions */
#define XLLP_GPIO_AF_KP_MKIN0			XLLP_GPIO_ALT_FN_1

/* Pin  101  alternate functions */
#define XLLP_GPIO_AF_KP_MKIN1			XLLP_GPIO_ALT_FN_1

/* Pin  102  alternate functions */
#define XLLP_GPIO_AF_KP_MKIN2			XLLP_GPIO_ALT_FN_1

/* Pin  103  alternate functions */
#define XLLP_GPIO_AF_KP_MKOUT0			XLLP_GPIO_ALT_FN_2

/* Pin  104  alternate functions */
#define XLLP_GPIO_AF_KP_MKOUT1			XLLP_GPIO_ALT_FN_2

/* Pin  105  alternate functions */
#define XLLP_GPIO_AF_KP_MKOUT2			XLLP_GPIO_ALT_FN_2

/* Pin  106  alternate functions */
#define XLLP_GPIO_AF_KP_MKOUT3			XLLP_GPIO_ALT_FN_2

/* Pin  107  alternate functions */
#define XLLP_GPIO_AF_KP_MKOUT4			XLLP_GPIO_ALT_FN_2

/* Pin  108  alternate functions */
#define XLLP_GPIO_AF_KP_MKOUT5			XLLP_GPIO_ALT_FN_2

/* Pin  109  alternate functions */
#define XLLP_GPIO_AF_MSSDIO				XLLP_GPIO_ALT_FN_2
#define XLLP_GPIO_AF_MMDAT1				XLLP_GPIO_ALT_FN_1

/* Pin  110  alternate functions */
#define XLLP_GPIO_AF_MMDAT2				XLLP_GPIO_ALT_FN_1

/* Pin  111  alternate functions */
#define XLLP_GPIO_AF_MMDAT3				XLLP_GPIO_ALT_FN_1

/* Pin  112  alternate functions */
#define XLLP_GPIO_AF_MMCMD				XLLP_GPIO_ALT_FN_1
#define XLLP_GPIO_AF_MSINS				XLLP_GPIO_ALT_FN_2

/* Pin  113  alternate functions */
#define XLLP_GPIO_AF_I2S_SYSCLK			XLLP_GPIO_ALT_FN_1
#define XLLP_GPIO_AF_AC97_nRESET		XLLP_GPIO_ALT_FN_2

/* Pin  114  alternate functions */
#define XLLP_GPIO_AF_UVS0				XLLP_GPIO_ALT_FN_2

/* Pin  114  alternate functions */
#define XLLP_GPIO_AF_CIF_DD1			XLLP_GPIO_ALT_FN_1

/* Pin  115  alternate functions */
#define XLLP_GPIO_AF_U_EN				XLLP_GPIO_ALT_FN_1

/* Pin  115  alternate functions */
#define XLLP_GPIO_AF_CIF_DD3			XLLP_GPIO_ALT_FN_2

/* Pin  116  alternate functions */
#define XLLP_GPIO_AF_U_DET				XLLP_GPIO_ALT_FN_3

/* Pin  116  alternate functions */
#define XLLP_GPIO_AF_CIF_DD2			XLLP_GPIO_ALT_FN_1

/* Pin  117  alternate functions */
#define XLLP_GPIO_AF_SCL				XLLP_GPIO_ALT_FN_1

/* Pin  118  alternate functions */
#define XLLP_GPIO_AF_SDA				XLLP_GPIO_ALT_FN_1

/* Pin  119  alternate functions */
#define XLLP_GPIO_AF_USBHPWR2			XLLP_GPIO_ALT_FN_1

/* Pin  120  alternate functions */
#define XLLP_GPIO_AF_USBHPEN2			XLLP_GPIO_ALT_FN_2


/* END of alternate function values for each GPIO */
/************************************************************************/
// GPIO register reserved and valid bit masks

#define XLLP_GPIO_GPLR0_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GPLR0_VLD_MSK (~(XLLP_GPIO_GPLR0_RESERVED_BITS))
#define XLLP_GPIO_GPLR1_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GPLR1_VLD_MSK (~(XLLP_GPIO_GPLR1_RESERVED_BITS))
#define XLLP_GPIO_GPLR2_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GPLR2_VLD_MSK (~(XLLP_GPIO_GPLR2_RESERVED_BITS))
#define XLLP_GPIO_GPLR3_RESERVED_BITS 0xFE000000u
#define XLLP_GPIO_GPLR3_VLD_MSK (~(XLLP_GPIO_GPLR3_RESERVED_BITS))

#define XLLP_GPIO_GPDR0_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GPDR0_VLD_MSK (~(XLLP_GPIO_GPDR0_RESERVED_BITS))
#define XLLP_GPIO_GPDR1_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GPDR1_VLD_MSK (~(XLLP_GPIO_GPDR1_RESERVED_BITS))
#define XLLP_GPIO_GPDR2_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GPDR2_VLD_MSK (~(XLLP_GPIO_GPDR2_RESERVED_BITS))
#define XLLP_GPIO_GPDR3_RESERVED_BITS 0xFE000000u
#define XLLP_GPIO_GPDR3_VLD_MSK (~(XLLP_GPIO_GPDR3_RESERVED_BITS))

#define XLLP_GPIO_GPSR0_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GPSR0_VLD_MSK (~(XLLP_GPIO_GPSR0_RESERVED_BITS))
#define XLLP_GPIO_GPSR1_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GPSR1_VLD_MSK (~(XLLP_GPIO_GPSR1_RESERVED_BITS))
#define XLLP_GPIO_GPSR2_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GPSR2_VLD_MSK (~(XLLP_GPIO_GPSR2_RESERVED_BITS))
#define XLLP_GPIO_GPSR3_RESERVED_BITS 0xFE000000u
#define XLLP_GPIO_GPSR3_VLD_MSK (~(XLLP_GPIO_GPSR3_RESERVED_BITS))

#define XLLP_GPIO_GPCR0_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GPCR0_VLD_MSK (~(XLLP_GPIO_GPCR0_RESERVED_BITS))
#define XLLP_GPIO_GPCR1_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GPCR1_VLD_MSK (~(XLLP_GPIO_GPCR1_RESERVED_BITS))
#define XLLP_GPIO_GPCR2_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GPCR2_VLD_MSK (~(XLLP_GPIO_GPCR2_RESERVED_BITS))
#define XLLP_GPIO_GPCR3_RESERVED_BITS 0xFE000000u
#define XLLP_GPIO_GPCR3_VLD_MSK (~(XLLP_GPIO_GPCR3_RESERVED_BITS))

#define XLLP_GPIO_GRER0_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GRER0_VLD_MSK (~(XLLP_GPIO_GRER0_RESERVED_BITS))
#define XLLP_GPIO_GRER1_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GRER1_VLD_MSK (~(XLLP_GPIO_GRER1_RESERVED_BITS))
#define XLLP_GPIO_GRER2_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GRER2_VLD_MSK (~(XLLP_GPIO_GRER2_RESERVED_BITS))
#define XLLP_GPIO_GRER3_RESERVED_BITS 0xFE000000u
#define XLLP_GPIO_GRER3_VLD_MSK (~(XLLP_GPIO_GRER3_RESERVED_BITS))

#define XLLP_GPIO_GFER0_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GFER0_VLD_MSK (~(XLLP_GPIO_GFER0_RESERVED_BITS))
#define XLLP_GPIO_GFER1_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GFER1_VLD_MSK (~(XLLP_GPIO_GFER1_RESERVED_BITS))
#define XLLP_GPIO_GFER2_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GFER2_VLD_MSK (~(XLLP_GPIO_GFER2_RESERVED_BITS))
#define XLLP_GPIO_GFER3_RESERVED_BITS 0xFE000000u
#define XLLP_GPIO_GFER3_VLD_MSK (~(XLLP_GPIO_GFER3_RESERVED_BITS))

#define XLLP_GPIO_GEDR0_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GEDR0_VLD_MSK (~(XLLP_GPIO_GEDR0_RESERVED_BITS))
#define XLLP_GPIO_GEDR1_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GEDR1_VLD_MSK (~(XLLP_GPIO_GEDR1_RESERVED_BITS))
#define XLLP_GPIO_GEDR2_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GEDR2_VLD_MSK (~(XLLP_GPIO_GEDR2_RESERVED_BITS))
#define XLLP_GPIO_GEDR3_RESERVED_BITS 0xFE000000u
#define XLLP_GPIO_GEDR3_VLD_MSK (~(XLLP_GPIO_GEDR3_RESERVED_BITS))

#define XLLP_GPIO_GAFR0_L_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GAFR0_L_VLD_MSK (~(XLLP_GPIO_GAFR0_L_RESERVED_BITS))
#define XLLP_GPIO_GAFR0_U_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GAFR0_U_VLD_MSK (~(XLLP_GPIO_GAFR0_U_RESERVED_BITS))
#define XLLP_GPIO_GAFR1_L_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GAFR1_L_VLD_MSK (~(XLLP_GPIO_GAFR1_L_RESERVED_BITS))
#define XLLP_GPIO_GAFR1_U_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GAFR1_U_VLD_MSK (~(XLLP_GPIO_GAFR1_U_RESERVED_BITS))
#define XLLP_GPIO_GAFR2_L_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GAFR2_L_VLD_MSK (~(XLLP_GPIO_GAFR2_L_RESERVED_BITS))
#define XLLP_GPIO_GAFR2_U_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GAFR2_U_VLD_MSK (~(XLLP_GPIO_GAFR2_U_RESERVED_BITS))
#define XLLP_GPIO_GAFR3_L_RESERVED_BITS 0x00000000u
#define XLLP_GPIO_GAFR3_L_VLD_MSK (~(XLLP_GPIO_GAFR3_L_RESERVED_BITS))
#define XLLP_GPIO_GAFR3_U_RESERVED_BITS 0xFFFC0000u
#define XLLP_GPIO_GAFR3_U_VLD_MSK (~(XLLP_GPIO_GAFR3_U_RESERVED_BITS))

// END of GPIO register reserved and valid bit masks
/************************************************************************/

/* XLLP GPIO API typedefs */
/* Bulverde has four GPIO register banks */
/* For non-alternate function registers */

typedef enum 
{
    XLLP_GPIO_BANK_0,
    XLLP_GPIO_BANK_1,
    XLLP_GPIO_BANK_2,
    XLLP_GPIO_BANK_3
} XLLP_GPIO_REGISTER_BANK_T;  
      

/* Bulverde has eight half GPIO register banks */
/* For only alternate function registers */
typedef enum 
{
    XLLP_GPIO_HALF_BANK_0_L,
	XLLP_GPIO_HALF_BANK_0_U,
	XLLP_GPIO_HALF_BANK_1_L,
	XLLP_GPIO_HALF_BANK_1_U,
	XLLP_GPIO_HALF_BANK_2_L,
	XLLP_GPIO_HALF_BANK_2_U,
	XLLP_GPIO_HALF_BANK_3_L,
	XLLP_GPIO_HALF_BANK_3_U
} XLLP_GPIO_REGISTER_HALF_BANK_T;        


typedef enum
{
    XLLP_GPIO_ALT_FN_0 = 0x0,
    XLLP_GPIO_ALT_FN_1 = 0x1,
    XLLP_GPIO_ALT_FN_2 = 0x2,
    XLLP_GPIO_ALT_FN_3 = 0x3
} XLLP_GPIO_ALT_FUNC_T;

#ifdef __cplusplus
extern "C" {
#endif

XLLP_UINT32_T XllpGpioGetState (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPin);
XLLP_UINT32_T XllpGpioGetDirection (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPin);
void XllpGpioSetDirectionIn (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPinArray[]);
void XllpGpioSetDirectionOut (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPinArray[]);
void XllpGpioSetOutputState1 (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPinArray[]);
void XllpGpioSetOutput0 (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPinArray[]);
XLLP_UINT32_T XllpGpioGetRisingDetectEnable (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPin);
void XllpGpioSetRisingDetectDisable (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPinArray[]);
void XllpGpioSetRisingDetectEnable (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPinArray[]);
XLLP_UINT32_T XllpGpioGetFallingDetectEnable (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPin);
void XllpGpioSetFallingEdgeDetectDisable (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPinArray[]);
void XllpGpioSetFallingEdgeDetectEnable (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPinArray[]);
XLLP_UINT32_T XllpGpioGetEdgeDetectStatus (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPin);
void XllpGpioClearEdgeDetectStatus (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPinArray[]);
XLLP_UINT32_T XllpGpioGetAlternateFn (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPin);
void XllpGpioSetAlternateFn (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPinArray[], XLLP_UINT32_T aAfValueArray[]);
void XllpGpioClearAlternateFn (P_XLLP_GPIO_T pGPIO, XLLP_UINT32_T aGpioPinArray[]);
/* XLLP GPIO Function Prototypes - None */

#ifdef __cplusplus
};
#endif


#endif //__GPIO_H__