📄 xllp_gpio.h
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#define XLLP_GPIO_BIT_AC97_RESET_n ( XLLP_BIT_17 )
#define XLLP_GPIO_BIT_I2S_SYSCLK ( XLLP_BIT_17 )
#define XLLP_GPIO_BIT_UVS0 ( XLLP_BIT_18 )
#define XLLP_GPIO_BIT_CIF_DD1 ( XLLP_BIT_18 )
#define XLLP_GPIO_BIT_U_EN ( XLLP_BIT_19 )
#define XLLP_GPIO_BIT_CIF_DD3 ( XLLP_BIT_19 )
#define XLLP_GPIO_BIT_U_DET ( XLLP_BIT_20 )
#define XLLP_GPIO_BIT_CIF_DD2 ( XLLP_BIT_20 )
#define XLLP_GPIO_BIT_SCL ( XLLP_BIT_21 )
#define XLLP_GPIO_BIT_SDA ( XLLP_BIT_22 )
/******* End of GPIO Pin Bit Position ********/
/*=================================================================*/
/* BEGIN of alternate function values for each GPIO -- in BIT-WISE */
//
//
/* Pin 11 alternate functions */
#define XLLP_GPIO_AF_BIT_SSPRXD2 (0x2u << 22)
#define XLLP_GPIO_AF_BIT_SSPRXD2_MASK (0x3u << 22)
/* Pin 12 alternate functions */
#define XLLP_GPIO_AF_BIT_CIF_DD7 (0x2u << 24)
#define XLLP_GPIO_AF_BIT_CIF_DD7_MASK (0x3u << 24)
/* Pin 13 alternate functions */
#define XLLP_GPIO_AF_BIT_SSPTXD2 (XLLP_BIT_26)
#define XLLP_GPIO_AF_BIT_SSPTXD2_MASK (0x3u << 26)
/* Pin 14 alternate functions */
#define XLLP_GPIO_AF_BIT_L_VSYNC (XLLP_BIT_28)
#define XLLP_GPIO_AF_BIT_L_VSYNC_MASK (0x3u << 28)
/* Pin 15 alternate functions */
#define XLLP_GPIO_AF_BIT_nCS1 (0x2u << 30)
#define XLLP_GPIO_AF_BIT_nCS1_MASK (0x3u << 30)
/* Pin 16 alternate functions */
#define XLLP_GPIO_AF_BIT_PWM_OUT0 (0x2u << 0)
#define XLLP_GPIO_AF_BIT_PWM_OUT0_MASK (0x3u << 0)
/* Pin 17 alternate functions */
#define XLLP_GPIO_AF_BIT_PWM_OUT1 (0x2u << 2)
#define XLLP_GPIO_AF_BIT_PWM_OUT1_MASK (0x3u << 2)
/* Pin 17 alternate functions */
#define XLLP_GPIO_AF_BIT_CIF_DD6 (0x2u << 2)
#define XLLP_GPIO_AF_BIT_CIF_DD6_MASK (0x3u << 2)
/* Pin 18 alternate functions */
#define XLLP_GPIO_AF_BIT_RDY (XLLP_BIT_4)
#define XLLP_GPIO_AF_BIT_RDY_MASK (0x3u << 4)
/* Pin 19 alternate functions */
#define XLLP_GPIO_AF_BIT_L_CS (0x2u << 6)
#define XLLP_GPIO_AF_BIT_L_CS_MASK (0x3u << 6)
/* Pin 20 alternate functions */
#define XLLP_GPIO_AF_BIT_MBREQ (0x2u << 8)
#define XLLP_GPIO_AF_BIT_MBREQ_MASK (0x3u << 8)
/* Pin 21 alternate functions */
#define XLLP_GPIO_AF_BIT_MBGNT (0x3u << 10)
#define XLLP_GPIO_AF_BIT_MBGNT_MASK (0x3u << 10)
/* Pin 22 alternate functions */
#define XLLP_GPIO_AF_BIT_SSPCLK2 (0x3u << 12)
#define XLLP_GPIO_AF_BIT_SSPCLK2_MASK (0x3u << 12)
/* Pin 23 alternate functions */
#define XLLP_GPIO_AF_BIT_CIF_MCLK (XLLP_BIT_14)
#define XLLP_GPIO_AF_BIT_CIF_MCLK_MASK (0x3u << 14)
/* Pin 24 alternate functions */
#define XLLP_GPIO_AF_BIT_CIF_FV (XLLP_BIT_16)
#define XLLP_GPIO_AF_BIT_CIF_FV_MASK (0x3u << 16)
/* Pin 25 alternate functions */
#define XLLP_GPIO_AF_BIT_CIF_LV (XLLP_BIT_18)
#define XLLP_GPIO_AF_BIT_CIF_LV_MASK (0x3u << 18)
/* Pin 26 alternate functions */
#define XLLP_GPIO_AF_BIT_CIF_PCLK (0x2u << 20)
#define XLLP_GPIO_AF_BIT_CIF_PCLK_MASK (0x3u << 20)
/* Pin 27 alternate functions */
#define XLLP_GPIO_AF_BIT_CIF_DD0 (0x3u << 22)
#define XLLP_GPIO_AF_BIT_CIF_DD0_MASK (0x3u << 22)
/* Pin 28 alternate functions */
#define XLLP_GPIO_AF_BIT_AC97_BITCLK (XLLP_BIT_24)
#define XLLP_GPIO_AF_BIT_AC97_BITCLK_MASK (0x3u << 24)
#define XLLP_GPIO_AF_BIT_I2SBITCLK_IN (0x2u << 24)
#define XLLP_GPIO_AF_BIT_I2SBITCLK_IN_MASK (0x3u << 24)
#define XLLP_GPIO_AF_BIT_I2SBITCLK_OUT (XLLP_BIT_24)
#define XLLP_GPIO_AF_BIT_I2SBITCLK_OUT_MASK (0x3u << 24)
/* Pin 29 alternate functions */
#define XLLP_GPIO_AF_BIT_AC97_SDATA_IN_0 (XLLP_BIT_26)
#define XLLP_GPIO_AF_BIT_AC97_SDATA_IN_0_MASK (0x3u << 26)
#define XLLP_GPIO_AF_BIT_I2S_SDATA_IN (0x2u << 26)
#define XLLP_GPIO_AF_BIT_I2S_SDATA_IN_MASK (0x3u << 26)
#define XLLP_GPIO_AF_BIT_SSP2_SSPRXD2 (0x1u << 26)
#define XLLP_GPIO_AF_BIT_SSP2_SSPRXD2_MASK (0x3u << 26)
/* Pin 30 alternate functions */
#define XLLP_GPIO_AF_BIT_I2S_SDATA_OUT (XLLP_BIT_28)
#define XLLP_GPIO_AF_BIT_I2S_SDATA_OUT_MASK (0x3u << 28)
#define XLLP_GPIO_AF_BIT_AC97_SDATA_OUT (0x2u << 28)
#define XLLP_GPIO_AF_BIT_AC97_SDATA_OUT_MASK (0x3u << 28)
/* Pin 31 alternate functions */
#define XLLP_GPIO_AF_BIT_I2S_SYNC (XLLP_BIT_30)
#define XLLP_GPIO_AF_BIT_I2S_SYNC_MASK (0x3u << 30)
#define XLLP_GPIO_AF_BIT_AC97_SYNC (0x2u << 30)
#define XLLP_GPIO_AF_BIT_AC97_SYNC_MASK (0x3u << 30)
/* Pin 32 alternate functions */
#define XLLP_GPIO_AF_BIT_MSSCLK (XLLP_BIT_0)
#define XLLP_GPIO_AF_BIT_MSSCLK_MASK (0x3u << 0)
#define XLLP_GPIO_AF_BIT_MMCLK (0x2u << 0)
#define XLLP_GPIO_AF_BIT_MMCLK_MASK (0x3u << 0)
/* Pin 33 alternate functions */
#define XLLP_GPIO_AF_BIT_nCS5 (0x2u << 2)
#define XLLP_GPIO_AF_BIT_nCS5_MASK (0x3u << 2)
/* Pin 34 alternate functions */
#define XLLP_GPIO_AF_BIT_FFRXD (XLLP_BIT_4)
#define XLLP_GPIO_AF_BIT_FFRXD_MASK (0x3u << 4)
/* Pin 34 alternate functions */
#define XLLP_GPIO_AF_BIT_USB_P2_2 (XLLP_BIT_4)
#define XLLP_GPIO_AF_BIT_USB_P2_2_MASK (0x3u << 4)
/* Pin 35 alternate functions */
#define XLLP_GPIO_AF_BIT_FFCTS (XLLP_BIT_6)
#define XLLP_GPIO_AF_BIT_FFCTS_MASK (0x3u << 6)
/* Pin 35 alternate functions */
#define XLLP_GPIO_AF_BIT_USB_P2_1 (0x2u << 6)
#define XLLP_GPIO_AF_BIT_USB_P2_1_MASK (0x3u << 6)
/* Pin 36 alternate functions */
#define XLLP_GPIO_AF_BIT_FFDCD (XLLP_BIT_8)
#define XLLP_GPIO_AF_BIT_FFDCD_MASK (0x3u << 8)
/* Pin 36 alternate functions */
#define XLLP_GPIO_AF_BIT_USB_P2_4 (XLLP_BIT_8)
#define XLLP_GPIO_AF_BIT_USB_P2_4_MASK (0x3u << 8)
/* Pin 36 alternate functions */
#define XLLP_GPIO_AF_BIT_SSPSCLK2 (0x2u << 8)
#define XLLP_GPIO_AF_BIT_SSPSCLK2_MASK (0x3u << 8)
/* Pin 37 alternate functions */
#define XLLP_GPIO_AF_BIT_FFDSR (XLLP_BIT_10)
#define XLLP_GPIO_AF_BIT_FFDSR_MASK (0x3u << 10)
/* Pin 37 alternate functions */
#define XLLP_GPIO_AF_BIT_SSPSFRM2 (0x2u << 10)
#define XLLP_GPIO_AF_BIT_SSPSFRM2_MASK (0x3u << 10)
/* Pin 38 alternate functions */
#define XLLP_GPIO_AF_BIT_FFRI (XLLP_BIT_12)
#define XLLP_GPIO_AF_BIT_FFRI_MASK (0x3u << 12)
/* Pin 38 alternate functions */
#define XLLP_GPIO_AF_BIT_USB_P2_3 (0x3u << 12)
#define XLLP_GPIO_AF_BIT_USB_P2_3_MASK (0x3u << 12)
/* Pin 39 alternate functions */
#define XLLP_GPIO_AF_BIT_FFTXD (0x2u << 14)
#define XLLP_GPIO_AF_BIT_FFTXD_MASK (0x3u << 14)
/* Pin 39 alternate functions */
#define XLLP_GPIO_AF_BIT_USB_P2_6 (XLLP_BIT_14)
#define XLLP_GPIO_AF_BIT_USB_P2_6_MASK (0x3u << 14)
/* Pin 40 alternate functions */
#define XLLP_GPIO_AF_BIT_FFDTR (0x2u << 16)
#define XLLP_GPIO_AF_BIT_FFDTR_MASK (0x3u << 16)
/* Pin 40 alternate functions */
#define XLLP_GPIO_AF_BIT_USB_P2_5 (0x3u << 16)
#define XLLP_GPIO_AF_BIT_USB_P2_5_MASK (0x3u << 16)
/* Pin 41 alternate functions */
#define XLLP_GPIO_AF_BIT_FFRTS (0x2u << 18)
#define XLLP_GPIO_AF_BIT_FFRTS_MASK (0x3u << 18)
/* Pin 42 alternate functions */
#define XLLP_GPIO_AF_BIT_BTRXD (XLLP_BIT_20)
#define XLLP_GPIO_AF_BIT_BTRXD_MASK (0x3u << 20)
/* Pin 43 alternate functions */
#define XLLP_GPIO_AF_BIT_BTTXD (0x2u << 22)
#define XLLP_GPIO_AF_BIT_BTTXD_MASK (0x3u << 22)
/* Pin 44 alternate functions */
#define XLLP_GPIO_AF_BIT_BTCTS (XLLP_BIT_24)
#define XLLP_GPIO_AF_BIT_BTCTS_MASK (0x3u << 24)
/* Pin 45 alternate functions */
#define XLLP_GPIO_AF_BIT_BTRTS (0x2u << 26)
#define XLLP_GPIO_AF_BIT_BTRTS_MASK (0x3u << 26)
/* Pin 46 alternate functions */
#define XLLP_GPIO_AF_BIT_ICP_RXD (XLLP_BIT_28)
#define XLLP_GPIO_AF_BIT_ICP_RXD_MASK (0x3u << 28)
#define XLLP_GPIO_AF_BIT_STD_RXD (0x2u << 28)
#define XLLP_GPIO_AF_BIT_STD_RXD_MASK (0x3u << 28)
/* Pin 47 alternate functions */
#define XLLP_GPIO_AF_BIT_ICP_TXD (0x2u << 30)
#define XLLP_GPIO_AF_BIT_ICP_TXD_MASK (0x3u << 30)
#define XLLP_GPIO_AF_BIT_STD_TXD (XLLP_BIT_30)
#define XLLP_GPIO_AF_BIT_STD_TXD_MASK (0x3u << 30)
/* Pin 48 alternate functions */
#define XLLP_GPIO_AF_BIT_BB_OB_DAT1 (XLLP_BIT_0)
#define XLLP_GPIO_AF_BIT_BB_OB_DAT1_MASK (0x3u << 0)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPOE (0x2u << 0)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPOE_MASK (0x3u << 0)
/* Pin 49 alternate functions */
#define XLLP_GPIO_AF_BIT_nPWE (0x2u << 2)
#define XLLP_GPIO_AF_BIT_nPWE_MASK (0x3u << 2)
/* Pin 50 alternate functions */
#define XLLP_GPIO_AF_BIT_BB_OB_DAT2 (XLLP_BIT_4)
#define XLLP_GPIO_AF_BIT_BB_OB_DAT2_MASK (0x3u << 4)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPIOR (0x2u << 4)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPIOR_MASK (0x3u << 4)
/* Pin 51 alternate functions */
#define XLLP_GPIO_AF_BIT_BB_OB_DAT3 (XLLP_BIT_6)
#define XLLP_GPIO_AF_BIT_BB_OB_DAT3_MASK (0x3u << 6)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPIOW (0x2u << 6)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPIOW_MASK (0x3u << 6)
/* Pin 52 alternate functions */
#define XLLP_GPIO_AF_BIT_BB_OB_CLK (XLLP_BIT_8)
#define XLLP_GPIO_AF_BIT_BB_OB_CLK_MASK (0x3u << 8)
/* Pin 52 alternate functions */
#define XLLP_GPIO_AF_BIT_SSPSCLK3 (0x2u << 8)
#define XLLP_GPIO_AF_BIT_SSPSCLK3_MASK (0x3u << 8)
/* Pin 53 alternate functions */
#define XLLP_GPIO_AF_BIT_BB_OB_STB (XLLP_BIT_10)
#define XLLP_GPIO_AF_BIT_BB_OB_STB_MASK (0x3u << 10)
/* Pin 54 alternate functions */
#define XLLP_GPIO_AF_BIT_BB_OB_WAIT (0x2u << 12)
#define XLLP_GPIO_AF_BIT_BB_OB_WAIT_MASK (0x3u << 12)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPCE2 (0x2u << 12)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPCE2_MASK (0x3u << 12)
/* Pin 55 alternate functions */
#define XLLP_GPIO_AF_BIT_BB_IB_DAT1 (0x2u << 14)
#define XLLP_GPIO_AF_BIT_BB_IB_DAT1_MASK (0x3u << 14)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPREG (0x2u << 14)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPREG_MASK (0x3u << 14)
/* Pin 56 alternate functions */
#define XLLP_GPIO_AF_BIT_PCMCIA_nPWAIT (XLLP_BIT_16)
#define XLLP_GPIO_AF_BIT_PCMCIA_nPWAIT_MASK (0x3u << 16)
#define XLLP_GPIO_AF_BIT_BB_IB_DAT2 (0x2u << 16)
#define XLLP_GPIO_AF_BIT_BB_IB_DAT2_MASK (0x3u << 16)
/* Pin 57 alternate functions */
#define XLLP_GPIO_AF_BIT_PCMCIA_nIOIS16 (XLLP_BIT_18)
#define XLLP_GPIO_AF_BIT_PCMCIA_nIOIS16_MASK (0x3u << 18)
#define XLLP_GPIO_AF_BIT_BB_IB_DAT3 (0x2u << 18)
#define XLLP_GPIO_AF_BIT_BB_IB_DAT3_MASK (0x3u << 18)
/* Pin 58 alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD0 (0x2u << 20)
#define XLLP_GPIO_AF_BIT_L_DD0_MASK (0x3u << 20)
/* Pin 59 alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD1 (0x2u << 22)
#define XLLP_GPIO_AF_BIT_L_DD1_MASK (0x3u << 22)
/* Pin 60 alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD2 (0x2u << 24)
#define XLLP_GPIO_AF_BIT_L_DD2_MASK (0x3u << 24)
/* Pin 61 alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD3 (0x2u << 26)
#define XLLP_GPIO_AF_BIT_L_DD3_MASK (0x3u << 26)
/* Pin 62 alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD4 (0x2u << 28)
#define XLLP_GPIO_AF_BIT_L_DD4_MASK (0x3u << 28)
/* Pin 63 alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD5 (0x2u << 30)
#define XLLP_GPIO_AF_BIT_L_DD5_MASK (0x3u << 30)
/* Pin 64 alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD6 (0x2u << 0)
#define XLLP_GPIO_AF_BIT_L_DD6_MASK (0x3u << 0)
/* Pin 65 alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD7 (0x2u << 2)
#define XLLP_GPIO_AF_BIT_L_DD7_MASK (0x3u << 2)
/* Pin 66 alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD8 (0x2u << 4)
#define XLLP_GPIO_AF_BIT_L_DD8_MASK (0x3u << 4)
/* Pin 67 alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD9 (0x2u << 6)
#define XLLP_GPIO_AF_BIT_L_DD9_MASK (0x3u << 6)
/* Pin 68 alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD10 (0x2u << 8)
#define XLLP_GPIO_AF_BIT_L_DD10_MASK (0x3u << 8)
/* Pin 69 alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD11 (0x2u << 10)
#define XLLP_GPIO_AF_BIT_L_DD11_MASK (0x3u << 10)
/* Pin 70 alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD12 (0x2u << 12)
#define XLLP_GPIO_AF_BIT_L_DD12_MASK (0x3u << 12)
/* Pin 71 alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD13 (0x2u << 14)
#define XLLP_GPIO_AF_BIT_L_DD13_MASK (0x3u << 14)
/* Pin 72 alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD14 (0x2u << 16)
#define XLLP_GPIO_AF_BIT_L_DD14_MASK (0x3u << 16)
/* Pin 73 alternate functions */
#define XLLP_GPIO_AF_BIT_L_DD15 (0x2u << 18)
#define XLLP_GPIO_AF_BIT_L_DD15_MASK (0x3u << 18)
/* Pin 74 alternate functions */
#define XLLP_GPIO_AF_BIT_L_FCLK_RD (0x2u << 20)
#define XLLP_GPIO_AF_BIT_L_FCLK_RD_MASK (0x3u << 20)
/* Pin 75 alternate functions */
#define XLLP_GPIO_AF_BIT_L_LCLK_A0 (0x2u << 22)
#define XLLP_GPIO_AF_BIT_L_LCLK_A0_MASK (0x3u << 22)
/* Pin 76 alternate functions */
#define XLLP_GPIO_AF_BIT_L_PCLK_WR (0x2u << 24)
#define XLLP_GPIO_AF_BIT_L_PCLK_WR_MASK (0x3u << 24)
/* Pin 77 alternate functions */
#define XLLP_GPIO_AF_BIT_L_BIAS (0x2u << 26)
#define XLLP_GPIO_AF_BIT_L_BIAS_MASK (0x3u << 26)
/* Pin 78 alternate functions */
#define XLLP_GPIO_AF_BIT_nCS2 (0x2u << 28)
#define XLLP_GPIO_AF_BIT_nCS2_MASK (0x3u << 28)
/* Pin 79 alternate functions */
#define XLLP_GPIO_AF_BIT_PCMCIA_PSKTSEL (XLLP_BIT_30)
#define XLLP_GPIO_AF_BIT_PCMCIA_PSKTSEL_MASK (0x3u << 30)
/* Pin 80 alternate functions */
#define XLLP_GPIO_AF_BIT_nCS4 (0x2u << 0)
#define XLLP_GPIO_AF_BIT_nCS4_MASK (0x3u << 0)
/* Pin 81 alternate functions */
#define XLLP_GPIO_AF_BIT_BB_OB_DAT0 (0x2u << 2)
#define XLLP_GPIO_AF_BIT_BB_OB_DAT0_MASK (0x3u << 2)
/* Pin 81 alternate functions */
#define XLLP_GPIO_AF_BIT_SSPTXD3 (XLLP_BIT_2)
#define XLLP_GPIO_AF_BIT_SSPTXD3_MASK (0x3u << 2)
/* Pin 82 alternate functions */
#define XLLP_GPIO_AF_BIT_BB_IB_DAT0 (0x2u << 4)
#define XLLP_GPIO_AF_BIT_BB_IB_DAT0_MASK (0x3u << 4)
/* Pin 82 alternate functions */
#define XLLP_GPIO_AF_BIT_SSPRXD3 (XLLP_BIT_4)
#define XLLP_GPIO_AF_BIT_SSPRXD3_MASK (0x3u << 4)
/* Pin 83 alternate functions */
#define XLLP_GPIO_AF_BIT_BB_IB_CLK (0x2u << 6)
#define XLLP_GPIO_AF_BIT_BB_IB_CLK_MASK (0x3u << 6)
/* Pin 83 alternate functions */
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