📄 xllp_gpio.h
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/******************************************************************************
**
** COPYRIGHT (C) 2001, 2002 Intel Corporation.
**
** This software as well as the software described in it is furnished under
** license and may only be used or copied in accordance with the terms of the
** license. The information in this file is furnished for informational use
** only, is subject to change without notice, and should not be construed as
** a commitment by Intel Corporation. Intel Corporation assumes no
** responsibility or liability for any errors or inaccuracies that may appear
** in this document or any software that may be provided in association with
** this document.
** Except as permitted by such license, no part of this document may be
** reproduced, stored in a retrieval system, or transmitted in any form or by
** any means without the express written consent of Intel Corporation.
**
** FILENAME: xllp_gpio.h
**
** PURPOSE: contains all GPIO specific macros, typedefs, and prototypes.
** Declares no storage.
**
**
******************************************************************************/
#ifndef __GPIO_H__
#define __GPIO_H__
#include "xllp_defs.h"
/**
GPIO Register Definitions
**/
typedef struct
{
XLLP_VUINT32_T GPLR0; /* Level Detect Reg. Bank 0 */
XLLP_VUINT32_T GPLR1; /* Level Detect Reg. Bank 1 */
XLLP_VUINT32_T GPLR2; /* Level Detect Reg. Bank 2 */
XLLP_VUINT32_T GPDR0; /* Data Direction Reg. Bank 0 */
XLLP_VUINT32_T GPDR1; /* Data Direction Reg. Bank 1 */
XLLP_VUINT32_T GPDR2; /* Data Direction Reg. Bank 2 */
XLLP_VUINT32_T GPSR0; /* Pin Output Set Reg. Bank 0 */
XLLP_VUINT32_T GPSR1; /* Pin Output Set Reg. Bank 1 */
XLLP_VUINT32_T GPSR2; /* Pin Output Set Reg. Bank 2 */
XLLP_VUINT32_T GPCR0; /* Pin Output Clr Reg. Bank 0 */
XLLP_VUINT32_T GPCR1; /* Pin Output Clr Reg. Bank 1 */
XLLP_VUINT32_T GPCR2; /* Pin Output Clr Reg. Bank 2 */
XLLP_VUINT32_T GRER0; /* Ris. Edge Detect Enable Reg. Bank 0 */
XLLP_VUINT32_T GRER1; /* Ris. Edge Detect Enable Reg. Bank 1 */
XLLP_VUINT32_T GRER2; /* Ris. Edge Detect Enable Reg. Bank 2 */
XLLP_VUINT32_T GFER0; /* Fal. Edge Detect Enable Reg. Bank 0 */
XLLP_VUINT32_T GFER1; /* Fal. Edge Detect Enable Reg. Bank 1 */
XLLP_VUINT32_T GFER2; /* Fal. Edge Detect Enable Reg. Bank 2 */
XLLP_VUINT32_T GEDR0; /* Edge Detect Status Reg. Bank 0 */
XLLP_VUINT32_T GEDR1; /* Edge Detect Status Reg. Bank 1 */
XLLP_VUINT32_T GEDR2; /* Edge Detect Status Reg. Bank 2 */
XLLP_VUINT32_T GAFR0_L; /* Alt. Function Select Reg.[ 0:15 ] */
XLLP_VUINT32_T GAFR0_U; /* Alt. Function Select Reg.[ 16:31 ] */
XLLP_VUINT32_T GAFR1_L; /* Alt. Function Select Reg.[ 32:47 ] */
XLLP_VUINT32_T GAFR1_U; /* Alt. Function Select Reg.[ 48:63 ] */
XLLP_VUINT32_T GAFR2_L; /* Alt. Function Select Reg.[ 64:79 ] */
XLLP_VUINT32_T GAFR2_U; /* Alt. Function Select Reg.[ 80:95 ] */
XLLP_VUINT32_T GAFR3_L; /* Alt. Function Select Reg.[ 96:111] */
XLLP_VUINT32_T GAFR3_U; /* Alt. Function Select Reg.[112:120] */
XLLP_VUINT32_T RESERVED1[35]; /* addr. offset 0x074-0x0fc */
XLLP_VUINT32_T GPLR3; /* Level Detect Reg. Bank 3 */
XLLP_VUINT32_T RESERVED2[2]; /* addr. offset 0x104-0x108 */
XLLP_VUINT32_T GPDR3; /* Data Direction Reg. Bank 3 */
XLLP_VUINT32_T RESERVED3[2]; /* addr. offset 0x110-0x114 */
XLLP_VUINT32_T GPSR3; /* Pin Output Set Reg. Bank 3 */
XLLP_VUINT32_T RESERVED4[2]; /* addr. offset 0x11c-0x120 */
XLLP_VUINT32_T GPCR3; /* Pin Output Clr Reg. Bank 3 */
XLLP_VUINT32_T RESERVED5[2]; /* addr. offset 0x128-0x12c */
XLLP_VUINT32_T GRER3; /* Ris. Edge Detect Enable Reg. Bank 3 */
XLLP_VUINT32_T RESERVED6[2]; /* addr. offset 0x134-0x138 */
XLLP_VUINT32_T GFER3; /* Fal. Edge Detect Enable Reg. Bank 3 */
XLLP_VUINT32_T RESERVED7[2]; /* addr. offset 0x140-0x144 */
XLLP_VUINT32_T GEDR3; /* Edge Detect Status Reg. Bank 3 */
} XLLP_GPIO_T, *P_XLLP_GPIO_T;
/* Begin of GPIO Pin Values */
#define XLLP_GPIO_0 0
#define XLLP_GPIO_1 1
#define XLLP_GPIO_SYS_EN 2
#define XLLP_GPIO_PWR_SCL 3
#define XLLP_GPIO_PWR_SDA 4
#define XLLP_GPIO_PWR_CAP0 5
#define XLLP_GPIO_PWR_CAP1 6
#define XLLP_GPIO_PWR_CAP2 7
#define XLLP_GPIO_PWR_CAP3 8
#define XLLP_GPIO_CLK_PIO 9
#define XLLP_GPIO_CLK_TOUT 10
#define XLLP_GPIO_SSPRXD2 11
#define XLLP_GPIO_CIF_DD7 12
#define XLLP_GPIO_SSPTXD2 13
#define XLLP_GPIO_L_VSYNC 14
#define XLLP_GPIO_nCS1 15
#define XLLP_GPIO_PWM_OUT0 16
#define XLLP_GPIO_PWM_OUT1 17
#define XLLP_GPIO_CIF_DD6 17
#define XLLP_GPIO_RDY 18
#define XLLP_GPIO_L_CS 19
#define XLLP_GPIO_MBREQ 20
#define XLLP_GPIO_MBGNT 21
#define XLLP_GPIO_SSPCLK2 22
#define XLLP_GPIO_CIF_MCLK 23
#define XLLP_GPIO_CIF_FV 24
#define XLLP_GPIO_CIF_LV 25
#define XLLP_GPIO_CIF_PCLK 26
#define XLLP_GPIO_CIF_DD0 27
#define XLLP_GPIO_AC97BITCLK 28
#define XLLP_GPIO_I2SBITCLK 28
#define XLLP_GPIO_AC97_SDATA_IN_0 29
#define XLLP_GPIO_I2S_SDATA_IN 29
#define XLLP_GPIO_I2S_SDATA_OUT 30
#define XLLP_GPIO_AC97_SDATA_OUT 30
#define XLLP_GPIO_I2S_SYNC 31
#define XLLP_GPIO_AC97_SYNC 31
#define XLLP_GPIO_MMCLK 32
#define XLLP_GPIO_MSSCLK 32
#define XLLP_GPIO_nCS5 33
#define XLLP_GPIO_FFRXD 34
#define XLLP_GPIO_USB_P2_2 34
#define XLLP_GPIO_FFCTS 35
#define XLLP_GPIO_USB_P2_1 35
#define XLLP_GPIO_FFDCD 36
#define XLLP_GPIO_USB_P2_4 36
#define XLLP_GPIO_FFDSR 37
#define XLLP_GPIO_FFRI 38
#define XLLP_GPIO_USB_P2_3 38
#define XLLP_GPIO_FFTXD 39
#define XLLP_GPIO_USB_P2_6 39
#define XLLP_GPIO_FFDTR 40
#define XLLP_GPIO_USB_P2_5 40
#define XLLP_GPIO_FFRTS 41
#define XLLP_GPIO_BTRXD 42
#define XLLP_GPIO_BTTXD 43
#define XLLP_GPIO_BTCTS 44
#define XLLP_GPIO_BTRTS 45
#define XLLP_GPIO_ICP_RXD 46
#define XLLP_GPIO_STD_RXD 46
#define XLLP_GPIO_ICP_TXD 47
#define XLLP_GPIO_STD_TXD 47
#define XLLP_GPIO_BB_OB_DAT1 48
#define XLLP_GPIO_PCMCIA_nPOE 48
#define XLLP_GPIO_nPWE 49
#define XLLP_GPIO_BB_OB_DAT2 50
#define XLLP_GPIO_PCMCIA_nPIOR 50
#define XLLP_GPIO_BB_OB_DAT3 51
#define XLLP_GPIO_PCMCIA_nPIOW 51
#define XLLP_GPIO_BB_OB_CLK 52
#define XLLP_GPIO_BB_OB_STB 53
#define XLLP_GPIO_BB_OB_WAIT 54
#define XLLP_GPIO_PCMCIA_nPCE2 54
#define XLLP_GPIO_BB_IB_DAT1 55
#define XLLP_GPIO_PCMCIA_nPREG 55
#define XLLP_GPIO_BB_IB_DAT2 56
#define XLLP_GPIO_PCMCIA_nPWAIT 56
#define XLLP_GPIO_BB_IB_DAT3 57
#define XLLP_GPIO_PCMCIA_nIOIS16 57
#define XLLP_GPIO_L_DD0 58
#define XLLP_GPIO_L_DD1 59
#define XLLP_GPIO_L_DD2 60
#define XLLP_GPIO_L_DD3 61
#define XLLP_GPIO_L_DD4 62
#define XLLP_GPIO_L_DD5 63
#define XLLP_GPIO_L_DD6 64
#define XLLP_GPIO_L_DD7 65
#define XLLP_GPIO_L_DD8 66
#define XLLP_GPIO_L_DD9 67
#define XLLP_GPIO_L_DD10 68
#define XLLP_GPIO_L_DD11 69
#define XLLP_GPIO_L_DD12 70
#define XLLP_GPIO_L_DD13 71
#define XLLP_GPIO_L_DD14 72
#define XLLP_GPIO_L_DD15 73
#define XLLP_GPIO_L_FCLK 74
#define XLLP_GPIO_L_LCLK 75
#define XLLP_GPIO_L_PCLK 76
#define XLLP_GPIO_L_BIAS 77
#define XLLP_GPIO_nCS2 78
#define XLLP_GPIO_PCMCIA_PSKTSEL 79
#define XLLP_GPIO_nCS4 80
#define XLLP_GPIO_BB_OB_DAT0 81
#define XLLP_GPIO_BB_IB_DAT0 82
#define XLLP_GPIO_BB_IB_CLK 83
#define XLLP_GPIO_BB_IB_STB 84
#define XLLP_GPIO_BB_IB_WAIT 85
#define XLLP_GPIO_PCMCIA_nPCE1 85
#define XLLP_GPIO_L_DD16 86
#define XLLP_GPIO_PCMCIA_nPCE1_1 86
#define XLLP_GPIO_L_DD17 87
#define XLLP_GPIO_PCMCIA_nPCE1_2 87
#define XLLP_GPIO_USBHPWR0 88
#define XLLP_GPIO_SSPFRM2 88
#define XLLP_GPIO_USBHPEN0 89
#define XLLP_GPIO_URST 90
#define XLLP_GPIO_CIF_DD4 90
#define XLLP_GPIO_UCLK 91
#define XLLP_GPIO_CIF_DD5 91
#define XLLP_GPIO_MMDAT0 92
#define XLLP_GPIO_MSBS 92
#define XLLP_GPIO_KP_DKIN0 93
#define XLLP_GPIO_KP_DKIN1 94
#define XLLP_GPIO_KP_MKIN6 95
#define XLLP_GPIO_KP_MKOUT6 96
#define XLLP_GPIO_KP_MKIN3 97
#define XLLP_GPIO_KP_MKIN4 98
#define XLLP_GPIO_KP_MKIN5 99
#define XLLP_GPIO_KP_MKIN0 100
#define XLLP_GPIO_KP_MKIN1 101
#define XLLP_GPIO_KP_MKIN2 102
#define XLLP_GPIO_KP_MKOUT0 103
#define XLLP_GPIO_KP_MKOUT1 104
#define XLLP_GPIO_KP_MKOUT2 105
#define XLLP_GPIO_KP_MKOUT3 106
#define XLLP_GPIO_KP_MKOUT4 107
#define XLLP_GPIO_KP_MKOUT5 108
#define XLLP_GPIO_MMDAT1 109
#define XLLP_GPIO_MSSDIO 109
#define XLLP_GPIO_MMDAT2 110
#define XLLP_GPIO_MMDAT3 111
#define XLLP_GPIO_MMCMD 112
#define XLLP_GPIO_MSINS 112
#define XLLP_GPIO_AC97_RESET_n 113
#define XLLP_GPIO_I2S_SYSCLK 113
#define XLLP_GPIO_UVS0 114
#define XLLP_GPIO_CIF_DD1 114
#define XLLP_GPIO_U_EN 115
#define XLLP_GPIO_CIF_DD3 115
#define XLLP_GPIO_U_DET 116
#define XLLP_GPIO_CIF_DD2 116
#define XLLP_GPIO_SCL 117
#define XLLP_GPIO_SDA 118
/* End of GPIO Pin Values */
/******* Begin of GPIO Pin Bit Position ********/
/* GPIO Pin Bank 0 */
#define XLLP_GPIO_BIT_0 ( XLLP_BIT_0 )
#define XLLP_GPIO_BIT_1 ( XLLP_BIT_1 )
#define XLLP_GPIO_BIT_SYS_EN ( XLLP_BIT_2 )
#define XLLP_GPIO_BIT_PWR_SCL ( XLLP_BIT_3 )
#define XLLP_GPIO_BIT_PWR_SDA ( XLLP_BIT_4 )
#define XLLP_GPIO_BIT_PWR_CAP0 ( XLLP_BIT_5 )
#define XLLP_GPIO_BIT_PWR_CAP1 ( XLLP_BIT_6 )
#define XLLP_GPIO_BIT_PWR_CAP2 ( XLLP_BIT_7 )
#define XLLP_GPIO_BIT_PWR_CAP3 ( XLLP_BIT_8 )
#define XLLP_GPIO_BIT_CLK_PIO ( XLLP_BIT_9 )
#define XLLP_GPIO_BIT_CLK_TOUT ( XLLP_BIT_10 )
#define XLLP_GPIO_BIT_SSPRXD2 ( XLLP_BIT_11 )
#define XLLP_GPIO_BIT_CIF_DD7 ( XLLP_BIT_12 )
#define XLLP_GPIO_BIT_SSPTXD2 ( XLLP_BIT_13 )
#define XLLP_GPIO_BIT_L_VSYNC ( XLLP_BIT_14 )
#define XLLP_GPIO_BIT_nCS1 ( XLLP_BIT_15 )
#define XLLP_GPIO_BIT_PWM_OUT0 ( XLLP_BIT_16 )
#define XLLP_GPIO_BIT_PWM_OUT1 ( XLLP_BIT_17 )
#define XLLP_GPIO_BIT_CIF_DD6 ( XLLP_BIT_17 )
#define XLLP_GPIO_BIT_RDY ( XLLP_BIT_18 )
#define XLLP_GPIO_BIT_L_CS ( XLLP_BIT_19 )
#define XLLP_GPIO_BIT_MBREQ ( XLLP_BIT_20 )
#define XLLP_GPIO_BIT_MBGNT ( XLLP_BIT_21 )
#define XLLP_GPIO_BIT_SSPCLK2 ( XLLP_BIT_22 )
#define XLLP_GPIO_BIT_CIF_MCLK ( XLLP_BIT_23 )
#define XLLP_GPIO_BIT_CIF_FV ( XLLP_BIT_24 )
#define XLLP_GPIO_BIT_CIF_LV ( XLLP_BIT_25 )
#define XLLP_GPIO_BIT_CIF_PCLK ( XLLP_BIT_26 )
#define XLLP_GPIO_BIT_CIF_DD0 ( XLLP_BIT_27 )
#define XLLP_GPIO_BIT_AC97BITCLK ( XLLP_BIT_28 )
#define XLLP_GPIO_BIT_I2SBITCLK ( XLLP_BIT_28 )
#define XLLP_GPIO_BIT_AC97_SDATA_IN_0 ( XLLP_BIT_29 )
#define XLLP_GPIO_BIT_I2S_SDATA_IN ( XLLP_BIT_29 )
#define XXLP_GPIO_BIT_SSP2_SSPRXD2 ( XLLP_BIT_29 )
#define XLLP_GPIO_BIT_I2S_SDATA_OUT ( XLLP_BIT_30 )
#define XLLP_GPIO_BIT_AC97_SDATA_OUT ( XLLP_BIT_30 )
#define XLLP_GPIO_BIT_I2S_SYNC ( XLLP_BIT_31 )
#define XLLP_GPIO_BIT_AC97_SYNC ( XLLP_BIT_31 )
/* GPIO Pin Bank 1 */
#define XLLP_GPIO_BIT_MMCLK ( XLLP_BIT_0 )
#define XLLP_GPIO_BIT_MSSCLK ( XLLP_BIT_0 )
#define XLLP_GPIO_BIT_nCS5 ( XLLP_BIT_1 )
#define XLLP_GPIO_BIT_FFRXD ( XLLP_BIT_2 )
#define XLLP_GPIO_BIT_USB_P2_2 ( XLLP_BIT_2 )
#define XLLP_GPIO_BIT_FFCTS ( XLLP_BIT_3 )
#define XLLP_GPIO_BIT_USB_P2_1 ( XLLP_BIT_3 )
#define XLLP_GPIO_BIT_FFDCD ( XLLP_BIT_4 )
#define XLLP_GPIO_BIT_USB_P2_4 ( XLLP_BIT_4 )
#define XLLP_GPIO_BIT_FFDSR ( XLLP_BIT_5 )
#define XLLP_GPIO_BIT_FFRI ( XLLP_BIT_6 )
#define XLLP_GPIO_BIT_USB_P2_3 ( XLLP_BIT_6 )
#define XLLP_GPIO_BIT_FFTXD ( XLLP_BIT_7 )
#define XLLP_GPIO_BIT_USB_P2_6 ( XLLP_BIT_7 )
#define XLLP_GPIO_BIT_FFDTR ( XLLP_BIT_8 )
#define XLLP_GPIO_BIT_USB_P2_5 ( XLLP_BIT_8 )
#define XLLP_GPIO_BIT_FFRTS ( XLLP_BIT_9 )
#define XLLP_GPIO_BIT_BTRXD ( XLLP_BIT_10 )
#define XLLP_GPIO_BIT_BTTXD ( XLLP_BIT_11 )
#define XLLP_GPIO_BIT_BTCTS ( XLLP_BIT_12 )
#define XLLP_GPIO_BIT_BTRTS ( XLLP_BIT_13 )
#define XLLP_GPIO_BIT_ICP_RXD ( XLLP_BIT_14 )
#define XLLP_GPIO_BIT_STD_RXD ( XLLP_BIT_14 )
#define XLLP_GPIO_BIT_ICP_TXD ( XLLP_BIT_15 )
#define XLLP_GPIO_BIT_STD_TXD ( XLLP_BIT_15 )
#define XLLP_GPIO_BIT_BB_OB_DAT1 ( XLLP_BIT_16 )
#define XLLP_GPIO_BIT_PCMCIA_nPOE ( XLLP_BIT_16 )
#define XLLP_GPIO_BIT_nPWE ( XLLP_BIT_17 )
#define XLLP_GPIO_BIT_BB_OB_DAT2 ( XLLP_BIT_18 )
#define XLLP_GPIO_BIT_PCMCIA_nPIOR ( XLLP_BIT_18 )
#define XLLP_GPIO_BIT_BB_OB_DAT3 ( XLLP_BIT_19 )
#define XLLP_GPIO_BIT_PCMCIA_nPIOW ( XLLP_BIT_19 )
#define XLLP_GPIO_BIT_BB_OB_CLK ( XLLP_BIT_20 )
#define XLLP_GPIO_BIT_BB_OB_STB ( XLLP_BIT_21 )
#define XLLP_GPIO_BIT_BB_OB_WAIT ( XLLP_BIT_22 )
#define XLLP_GPIO_BIT_PCMCIA_nPCE2 ( XLLP_BIT_22 )
#define XLLP_GPIO_BIT_BB_IB_DAT1 ( XLLP_BIT_23 )
#define XLLP_GPIO_BIT_PCMCIA_nPREG ( XLLP_BIT_23 )
#define XLLP_GPIO_BIT_BB_IB_DAT2 ( XLLP_BIT_24 )
#define XLLP_GPIO_BIT_PCMCIA_nPWAIT ( XLLP_BIT_24 )
#define XLLP_GPIO_BIT_BB_IB_DAT3 ( XLLP_BIT_25 )
#define XLLP_GPIO_BIT_PCMCIA_nIOIS16 ( XLLP_BIT_25 )
#define XLLP_GPIO_BIT_L_DD0 ( XLLP_BIT_26 )
#define XLLP_GPIO_BIT_L_DD1 ( XLLP_BIT_27 )
#define XLLP_GPIO_BIT_L_DD2 ( XLLP_BIT_28 )
#define XLLP_GPIO_BIT_L_DD3 ( XLLP_BIT_29 )
#define XLLP_GPIO_BIT_L_DD4 ( XLLP_BIT_30 )
#define XLLP_GPIO_BIT_L_DD5 ( XLLP_BIT_31 )
/* GPIO Pin Bank 2 */
#define XLLP_GPIO_BIT_L_DD6 ( XLLP_BIT_0 )
#define XLLP_GPIO_BIT_L_DD7 ( XLLP_BIT_1 )
#define XLLP_GPIO_BIT_L_DD8 ( XLLP_BIT_2 )
#define XLLP_GPIO_BIT_L_DD9 ( XLLP_BIT_3 )
#define XLLP_GPIO_BIT_L_DD10 ( XLLP_BIT_4 )
#define XLLP_GPIO_BIT_L_DD11 ( XLLP_BIT_5 )
#define XLLP_GPIO_BIT_L_DD12 ( XLLP_BIT_6 )
#define XLLP_GPIO_BIT_L_DD13 ( XLLP_BIT_7 )
#define XLLP_GPIO_BIT_L_DD14 ( XLLP_BIT_8 )
#define XLLP_GPIO_BIT_L_DD15 ( XLLP_BIT_9 )
#define XLLP_GPIO_BIT_L_FCLK ( XLLP_BIT_10 )
#define XLLP_GPIO_BIT_L_LCLK ( XLLP_BIT_11 )
#define XLLP_GPIO_BIT_L_PCLK ( XLLP_BIT_12 )
#define XLLP_GPIO_BIT_L_BIAS ( XLLP_BIT_13 )
#define XLLP_GPIO_BIT_nCS2 ( XLLP_BIT_14 )
#define XLLP_GPIO_BIT_PCMCIA_PSKTSEL ( XLLP_BIT_15 )
#define XLLP_GPIO_BIT_nCS4 ( XLLP_BIT_16 )
#define XLLP_GPIO_BIT_BB_OB_DAT0 ( XLLP_BIT_17 )
#define XLLP_GPIO_BIT_BB_IB_DAT0 ( XLLP_BIT_18 )
#define XLLP_GPIO_BIT_BB_IB_CLK ( XLLP_BIT_19 )
#define XLLP_GPIO_BIT_BB_IB_STB ( XLLP_BIT_20 )
#define XLLP_GPIO_BIT_BB_IB_WAIT ( XLLP_BIT_21 )
#define XLLP_GPIO_BIT_PCMCIA_nPCE1 ( XLLP_BIT_21 )
#define XLLP_GPIO_BIT_L_DD16 ( XLLP_BIT_22 )
#define XLLP_GPIO_BIT_PCMCIA_nPCE1_1 ( XLLP_BIT_22 )
#define XLLP_GPIO_BIT_L_DD17 ( XLLP_BIT_23 )
#define XLLP_GPIO_BIT_PCMCIA_nPCE1_2 ( XLLP_BIT_23 )
#define XLLP_GPIO_BIT_USBHPWR0 ( XLLP_BIT_24 )
#define XLLP_GPIO_BIT_SSPFRM2 ( XLLP_BIT_24 )
#define XLLP_GPIO_BIT_USBHPEN0 ( XLLP_BIT_25 )
#define XLLP_GPIO_BIT_URST ( XLLP_BIT_26 )
#define XLLP_GPIO_BIT_CIF_DD4 ( XLLP_BIT_26 )
#define XLLP_GPIO_BIT_UCLK ( XLLP_BIT_27 )
#define XLLP_GPIO_BIT_CIF_DD5 ( XLLP_BIT_27 )
#define XLLP_GPIO_BIT_MMDAT0 ( XLLP_BIT_28 )
#define XLLP_GPIO_BIT_MSBS ( XLLP_BIT_28 )
#define XLLP_GPIO_BIT_KP_DKIN0 ( XLLP_BIT_29 )
#define XLLP_GPIO_BIT_KP_DKIN1 ( XLLP_BIT_30 )
#define XLLP_GPIO_BIT_KP_MKIN6 ( XLLP_BIT_31 )
/* GPIO Pin Bank 3 */
#define XLLP_GPIO_BIT_KP_MKOUT6 ( XLLP_BIT_0 )
#define XLLP_GPIO_BIT_KP_MKIN3 ( XLLP_BIT_1 )
#define XLLP_GPIO_BIT_KP_MKIN4 ( XLLP_BIT_2 )
#define XLLP_GPIO_BIT_KP_MKIN5 ( XLLP_BIT_3 )
#define XLLP_GPIO_BIT_KP_MKIN0 ( XLLP_BIT_4 )
#define XLLP_GPIO_BIT_KP_MKIN1 ( XLLP_BIT_5 )
#define XLLP_GPIO_BIT_KP_MKIN2 ( XLLP_BIT_6 )
#define XLLP_GPIO_BIT_KP_MKOUT0 ( XLLP_BIT_7 )
#define XLLP_GPIO_BIT_KP_MKOUT1 ( XLLP_BIT_8 )
#define XLLP_GPIO_BIT_KP_MKOUT2 ( XLLP_BIT_9 )
#define XLLP_GPIO_BIT_KP_MKOUT3 ( XLLP_BIT_10 )
#define XLLP_GPIO_BIT_KP_MKOUT4 ( XLLP_BIT_11 )
#define XLLP_GPIO_BIT_KP_MKOUT5 ( XLLP_BIT_12 )
#define XLLP_GPIO_BIT_MMDAT1 ( XLLP_BIT_13 )
#define XLLP_GPIO_BIT_MSSDIO ( XLLP_BIT_13 )
#define XLLP_GPIO_BIT_MMDAT2 ( XLLP_BIT_14 )
#define XLLP_GPIO_BIT_MMDAT3 ( XLLP_BIT_15 )
#define XLLP_GPIO_BIT_MMCMD ( XLLP_BIT_16 )
#define XLLP_GPIO_BIT_MSINS ( XLLP_BIT_16 )
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