vd_regmap.c

X-scale 27x 平台

//
// Copyright (c) Chrontel Inc.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Chrontel end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.

Module Name:  
   vd_regmap.c

Abstract:  

Revision:
   11/11/02 Roger Yu, Create file  
   12/06/02 Roger Yu, Add OS Timer defines for delay_us() function

Notes: 
--*/


#include "chrontel.h"

// This array will be used for mapping register
REG_MAP  Xsl_MapReg[REGCAT_SIZE];


int MapRegisterZones( void )
{
	int i, j;
	int result = 0;

//@@@NOTE:
//  Currently we only map the following register regions. If more XScale registers need
//  be mapped, code need be added.
//
//  LCDREG=0, CLKREG, GPIOREG, I2CREG, TIMERREG, MEMCREG, PWMREG, BCRREG, OUTDEVREG , REGCAT_SIZE
//
	Xsl_MapReg[LCDREG].physical = (PVOID)PHYADR_LCDREG;
    Xsl_MapReg[LCDREG].xsladdr = XSLADR_LCDREG;
	Xsl_MapReg[LCDREG].base = NULL;
    //Xsl_MapReg[LCDREG].len = 0x200;
    Xsl_MapReg[LCDREG].len = 0x400;   // change to 0x400 to include LCDDMA Regs
/*
	Xsl_MapReg[LCDDMAREG].physical = (PVOID)PHYADR_LCDDMAREG;
    Xsl_MapReg[LCDDMAREG].xsladdr = XSLADR_LCDDMAREG;;
	Xsl_MapReg[LCDDMAREG].base = NULL;
    Xsl_MapReg[LCDDMAREG].len = 0x200;
*/
	Xsl_MapReg[CLKREG].physical = (PVOID)PHYADR_CLKREG;
    Xsl_MapReg[CLKREG].xsladdr = XSLADR_CLKREG;
	Xsl_MapReg[CLKREG].base = NULL;
    Xsl_MapReg[CLKREG].len = 0x200;

	Xsl_MapReg[GPIOREG].physical = (PVOID)PHYADR_GPIOREG;
    Xsl_MapReg[GPIOREG].xsladdr = XSLADR_GPIOREG;
	Xsl_MapReg[GPIOREG].base = NULL;
    Xsl_MapReg[GPIOREG].len = 0x200;

	Xsl_MapReg[I2CREG].physical = (PVOID)PHYADR_I2CREG;
    Xsl_MapReg[I2CREG].xsladdr = XSLADR_I2CREG;
	Xsl_MapReg[I2CREG].base = NULL;
    Xsl_MapReg[I2CREG].len = 0x200;

	Xsl_MapReg[TIMERREG].physical = (PVOID)PHYADR_TIMERREG;
    Xsl_MapReg[TIMERREG].xsladdr = XSLADR_TIMERREG;
	Xsl_MapReg[TIMERREG].base = NULL;
    Xsl_MapReg[TIMERREG].len = 0x200;

	Xsl_MapReg[MEMCREG].physical = (PVOID)PHYADR_MEMCREG;
    Xsl_MapReg[MEMCREG].xsladdr = XSLADR_MEMCREG;
	Xsl_MapReg[MEMCREG].base = NULL;
    Xsl_MapReg[MEMCREG].len = 0x200;

	Xsl_MapReg[PWMREG].physical = (PVOID)PHYADR_PWMREG;
    Xsl_MapReg[PWMREG].xsladdr = XSLADR_PWMREG;
	Xsl_MapReg[PWMREG].base = NULL;
    Xsl_MapReg[PWMREG].len = 0x200;

	Xsl_MapReg[BCRREG].physical = (PVOID)PHYADR_BCRREG;
    Xsl_MapReg[BCRREG].xsladdr = XSLADR_BCRREG;
	Xsl_MapReg[BCRREG].base = NULL;
    Xsl_MapReg[BCRREG].len = 0x200;

    for (i=0; i< REGCAT_SIZE-1; i++)
	{
		Xsl_MapReg[i].mapaddr = VirtualAllocCopy( Xsl_MapReg[i].len, &Xsl_MapReg[i].base, Xsl_MapReg[i].physical);
		//If error on mapping registers, we free the mapped region and return ERROE
		if (NULL==Xsl_MapReg[i].mapaddr) {
			for (j=0; j<i; j++) {
				VirtualFree( (LPVOID)Xsl_MapReg[j].base, Xsl_MapReg[j].len, MEM_RELEASE);
			}
			return -1;
		}
	}

// Initialize I2C unit here
	{
        volatile PCLKMAN_REGS clkman;

        clkman = (volatile PCLKMAN_REGS)Xsl_MapReg[CLKREG].mapaddr;
		clkman->cken |= 0x4000;  // enable I2C unit clock
	    I2CInitialize();
	}
	return 0;
}


int UnmapRegisterZones( void )
{
	int j;

	for (j=0; j<REGCAT_SIZE-1; j++) {
		if (Xsl_MapReg[j].base)
		 VirtualFree( (LPVOID)Xsl_MapReg[j].base, 0, MEM_RELEASE);
	}
	return 0;
}