phyaddr.h

X-scale 27x 平台

//
// Copyright (c) Chrontel Inc.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Chrontel end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.

Module Name:  
   phyaddr.h
   
Abstract:  
   Holds definitions for XScale Register on the physical address mapping in BSP board.

Revision:
    01/18/03,  Roger Yu, Create File from old libi2c.h   
Notes: 

*/

#ifndef _PHYADDR_H
#define _PHYADDR_H	


	
	#ifdef __cplusplus
extern "C" {
	#endif


typedef enum {
	LCDREG=0, CLKREG, GPIOREG, I2CREG, TIMERREG, MEMCREG, PWMREG, BCRREG, OUTDEVREG , REGCAT_SIZE
} REG_CATALOG;

typedef struct {
	PVOID  physical;  // Physical Address assign by Kernel MMC
	PVOID  base;      // Mapped virtual address iin page boundary
	PVOID  mapaddr;   // Mapped virtual address
        DWORD  len;       // Mapping length in BYTE 
	DWORD  xsladdr;   // register address defined in XScale processor
}  REG_MAP, *PREG_MAP;

// @@@NOTE:  (Roger Yu)
// The following physical address for the registers is determined by the
// OEMAddressTable and the XScale data sheet.
// Since the OEMAddressTable is different from different vendor's system,
// change the value according to the system.
//

//@@##================== Change from here =====================

    // Video DMA Memory
//\\//\\//\\//
	//for CE4.1 Lubbock BSP
//#define PHYADR_LCD_FRAME_MEMORY_ORIG 0xA3C97000
	//for CE4.2 Lubbock BSP
#define PHYADR_LCD_FRAME_MEMORY_ORIG 0xA3D00000

// For 1024x768x2=0x180000, 2 frame need 0x300000 plus 30h for LCD DMA scriptor
//     800x600x2=0xEA600
//     640x480x2=0x96000 
#define PHYADR_LCD_FRAME_BUFFER_SIZE  0x96000

// XScale Register as defined in MemMap.inc
#define UC_ADDR_PERIF_REG		0xA6200000    // 0x4000_0000
#define UC_ADDR_LCDC_REG		0xB8200000    // 0x4400_0000
#define UC_ADDR_MEMC_REG		0xA6100000    // 0x4800_0000

//@@##=================== End of Change =======================
//
//>>>>> DPBXA250 System Board <<<<<<
//>>>>> If you use same seeting as Intel Lubbock or Sandgate, then no change here
//
    // XScale LCD Controller register 
#define PHYADR_LCDREG     (UC_ADDR_LCDC_REG)    // 0x44000000
#define XSLADR_LCDREG     0x44000000
  // XScale LCD DMA control register (DMA0, DMA1)
//#define PHYADR_LCDDMAREG  0xB8200200    // 0x44000200
    //  XScale Registers Clock control (L,N,M value) 
#define PHYADR_CLKREG     (UC_ADDR_PERIF_REG+0x01300000)    // 0x41300000
#define XSLADR_CLKREG     0x41300000
    //  XScale Regiters to control GPIO pins
#define PHYADR_GPIOREG    (UC_ADDR_PERIF_REG+0x00E00000)    // 0x40E00000
#define XSLADR_GPIOREG    0x40E00000
    //  XScale Regiters to control I2C function
#define PHYADR_I2CREG     (UC_ADDR_PERIF_REG+0x00301680)    // 0x40301680
#define XSLADR_I2CREG     0x40301680
    //  XScale Regiters to control I2C function
#define PHYADR_TIMERREG     (UC_ADDR_PERIF_REG+0x00A00000)    // 0x40A00000
#define XSLADR_TIMERREG     0x40A00000
    //  XScale Regiters to MEM Controller Register function
#define PHYADR_MEMCREG     (UC_ADDR_MEMC_REG)     // 0x4800_0000
#define XSLADR_MEMCREG     0x48000000

    //  XScale Regiters to PWM Controller Register function
#define PHYADR_PWMREG     (UC_ADDR_PERIF_REG+0x00B00000)     // 0x40B0_0000
#define XSLADR_PWMREG     0x40B00000

    //  Board Control Registers related to Display control 
    //@@@NOTE: system & board dependent.
#define PHYADR_BCRREG     0xBE300000    // 0x0800_0000  CS2
#define XSLADR_BCRREG     0x08000000

#define PHYADR_LCD_FRAME_MEMORY PHYADR_LCD_FRAME_MEMORY_ORIG
//----------------------------------------------------\\
//|  palette    |   Frame buffer  |  DMA descriptor  | 
//----------------------------------------------------

    // LCD Palette Size (8bpp:200h/4bpp:20h/1bpp:4h )
#define PHYADR_LCD_PALETTE_SIZE 0x20
    // LCD Palette Buffer (200h bytes)

#define PHYADR_LCD_PALETTE_BUFFER (PHYADR_LCD_FRAME_MEMORY)

#define PHYADR_LCD_FRAME_BUFFER  (PHYADR_LCD_PALETTE_BUFFER + PHYADR_LCD_PALETTE_SIZE)

    // LCD DMA Descriptor PhyAddr
#define PHYADR_LCD_DMADESC      (PHYADR_LCD_FRAME_BUFFER+PHYADR_LCD_FRAME_BUFFER_SIZE)



// This array will be used for mapping register
extern REG_MAP  Xsl_MapReg[REGCAT_SIZE];


#define ADR_CCCR     (PHYADR_CLKREG + 0x0)
#define ADR_MDREFR   (PHYADR_MEMCREG + 0x04)
#define ADR_OSCR     (PHYADR_TIMERREG + 0x10)


#ifdef __cplusplus
}     // extern "C"
#endif


#endif  // _PHYADDR_H