xsli2c.h

X-scale 27x 平台

//
// Copyright (c) Chrontel Inc.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Chrontel end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
// Module Name
//    xsli2c.h
// 
// Abstract
//    XSCALE I2C Register Bits Definitions
//
// Revision
//    11/27/02 Created by Roger Yu.
//

#ifndef __XSLI2C_H
#define __XSLI2C_H

//IBMR  I2C Bus Monitor Register =0x40301680
#define I2C_IBMR_SDAS	0x00000001  //SDA Status: This bit continuously reflects the value of the SDA pin
#define I2C_IBMR_SCLS	0x00000002  //SCL Status: This bit continuously reflects the value of the SCL pin

//IDBR  I2C Data Buffer Register -IDBR = 0x40301688
#define I2C_IDBR_IDB(n)  ((n) & 0xFF)	//I2C Data Buffer: Buffer for I2C bus send/receive data.

//ICR   I2C Control Register =0x40301690
#define I2C_ICR_START	0x00000001  //START
#define I2C_ICR_STOP	0x00000002  //STOP:
#define I2C_ICR_ACKNAK	0x00000004	//ACK/NAK Control:
#define I2C_ICR_TB		0x00000008	//Transfer Byte:
#define I2C_ICR_MA		0x00000010	//Master Abort:
#define I2C_ICR_SCLE	0x00000020	//SCL Enable:
#define I2C_ICR_IUE		0x00000040	//I2C Unit Enable:
#define I2C_ICR_GCD		0x00000080	//General Call Disable:
#define I2C_ICR_ITEIE	0x00000100	//IDBR Transmit Empty Interrupt Enable:
#define I2C_ICR_IRFIE	0x00000200	//IDBR Receive Full Interrupt Enable:
#define I2C_ICR_BEIE	0x00000400	//Bus Error Interrupt Enable:
#define I2C_ICR_SSDIE	0x00000800	//Slave STOP Detected Interrupt Enable:
#define I2C_ICR_ALDIE	0x00001000	//Arbitration Loss Detected Interrupt Enable:
#define I2C_ICR_SADIE	0x00002000	//Slave Address Detected Interrupt Enable:
#define I2C_ICR_UR		0x00004000	//Unit Reset:
#define I2C_ICR_FM		0x00008000	//Fast Mode:


//ISR   I2C Status Register = 0x4030_1698
#define I2C_ISR_RWM		0x00000001	//Read/Write Mode:
#define I2C_ISR_ACKNACK	0x00000002	//ACK/NAK Status:
#define I2C_ISR_UB		0x00000004	//Unit Busy:
#define I2C_ISR_IBB		0x00000008	//I2C Bus Busy:
#define I2C_ISR_SSD		0x00000010	//Slave STOP Detected:
#define I2C_ISR_ALD		0x00000020	//Arbitration Loss Detected:
#define I2C_ISR_ITE		0x00000040	//IDBR Transmit Empty:
#define I2C_ISR_IRF		0x00000080	//IDBR Receive Full:
#define I2C_ISR_GCAD	0x00000100	//General Call Address Detected:
#define I2C_ISR_SAD		0x00000200	//Slave Address Detected:
#define I2C_ISR_BED		0x00000400	//Bus Error Detected:


//ISAR   I2C Slave Address Register- 4030_16A0
#define I2C_ISAR_ISA8(n)	((n)>>1)   // For 8bit I2C address
#define I2C_ISAR_ISA(n)	    ((n))      // 7 bit I2C Address


//I2C Initialization & control
#define I2C_IDX_TWOBYTE  0x80000000

#endif