vdk-ts201.ldf

Visual DSP++ VDK的应用举例

/*
** Default LDF for a VDK project on the ADSP-TS201.
** 

** Libsim provides fast, mostly host emulated IO only supported by
** the simulator. The libio library provides IO processing (including
** file support) mostly done by the TigerSHARC target that is supported
** by the emulator and simulator. Libio together with libsim is the
** default used, but if __USING_LIBSIM is defined only libsim will be used.
**   From the driver command line, use options,
**          "-flags-link -MD__USING_LIBSIM=1"
**   in the IDDE, add -MD__USING_LIBSIM=1 to the linker additional
**   options

*/

// Setup the architecture
ARCHITECTURE(ADSP-TS201)

// Include the VDK preprocessor macros
#define VDK_LDF_
#include "VDK.h"

// Setup the VDK library preprocessor macros
#if VDK_INSTRUMENTATION_LEVEL_==2
#define VDK_IFLAG_ i
#elif VDK_INSTRUMENTATION_LEVEL_==1
#define VDK_IFLAG_ e
#else
#define VDK_IFLAG_ n
#endif

  #ifdef __TS_BYTE_ADDRESS
    #define RT_LIB_NAME(x) lib ## x ## _BA.dlb
    #define RT_OBJ_NAME(x) ts_ ## x ## _BA.doj
      #ifdef __ADI_LIBEH__
        #define RT_LIB_NAME_EH(x) lib ## x ## _X_MT_BA.dlb
      #else
        #define RT_LIB_NAME_EH(x) lib ## x ## _MT_BA.dlb
      #endif
  #else
    #define RT_LIB_NAME(x) lib ## x ## .dlb
    #define RT_OBJ_NAME(x) ts_ ## x ## .doj
      #ifdef __ADI_LIBEH__
        #define RT_LIB_NAME_EH(x) lib ## x ## _X_MT.dlb
      #else
        #define RT_LIB_NAME_EH(x) lib ## x ## _MT.dlb
      #endif
  #endif

   $MEMINIT = meminit_ts20x.doj;

#ifndef __USING_LIBSIM

$BASE_LIBRARIES = RT_LIB_NAME(c_ts201_mt), RT_LIB_NAME(io_ts201_mt), RT_LIB_NAME(dsp_ts201), RT_LIB_NAME(x_TS201_mt), RT_LIB_NAME_EH(cpp_ts201), RT_LIB_NAME_EH(cpprt_ts201), libsim_TS201.dlb, $MEMINIT, RT_OBJ_NAME(exit_cpp_TS201_mt);

#else

$BASE_LIBRARIES = RT_LIB_NAME(c_ts201_mt), RT_LIB_NAME(dsp_ts201), RT_LIB_NAME(x_TS201_mt), RT_LIB_NAME_EH(cpp_ts201), RT_LIB_NAME_EH(cpprt_ts201), libsim_TS201.dlb, $MEMINIT, RT_OBJ_NAME(exit_cpp_TS201_mt);

#endif

  #ifdef __TS_BYTE_ADDRESS
    #define VDK_LIB_NAME_MACRO_(x) vdk- ## x ## -TS2XX_BA.dlb
    #define VDK_LIB_NAME_(x) VDK_LIB_NAME_MACRO_(x)
    $LIBS = TMK-TS2XX_BA.dlb, VDK-CORE-TS201_BA.dlb, /* HEAP LIBS */ VDK_LIB_NAME_(VDK_IFLAG_), $BASE_LIBRARIES;
  #else // __TS_BYTE_ADDRESS
    #define VDK_LIB_NAME_MACRO_(x) vdk- ## x ## -TS2XX.dlb
    #define VDK_LIB_NAME_(x) VDK_LIB_NAME_MACRO_(x)
    $LIBS = TMK-TS2XX.dlb, VDK-CORE-TS201.dlb, /* HEAP LIBS */ VDK_LIB_NAME_(VDK_IFLAG_), $BASE_LIBRARIES;
  #endif // __TS_BYTE_ADDRESS

// Libraries from the command line are included in COMMAND_LINE_OBJECTS.
$OBJS = RT_OBJ_NAME(hdr_cpp_TS201_mt), $COMMAND_LINE_OBJECTS;

// List of objects and libraries which prefer internal memory as
// specified by prefersMem attribute.
$OBJS_LIBS_INTERNAL =
   $OBJS{prefersMem("internal")},
   $LIBS{prefersMem("internal")}
   ;

// List of objects and libraries which don't have a preference for
// external memory as specified by prefersMem attribute.
$OBJS_LIBS_NOT_EXTERNAL =
   $OBJS{!prefersMem("external")},
   $LIBS{!prefersMem("external")}
   ;

// Internal memory blocks are 0x20000 (128k)

PROCESSOR p0
{

  RESOLVE( _____system_start, 0x00000000 )
  KEEP( _main, ___ctor_end,
	_kMaxNumThreads__3VDK,_kMaxNumActiveSemaphores__3VDK,
	_g_Sem_ThreadBaseOffset__3VDK ,_kMaxNumActiveDevFlags__3VDK ,
	_kMaxNumActiveMessages__3VDK,  _kMaxNumActiveMemoryPools__3VDK,
	_kNumEvents__3VDK, _kNumEventBits__3VDK)

  OUTPUT( $COMMAND_LINE_OUTPUT_FILE )

  MEMORY
  {
#if __SILICON_REVISION__ < 0x100 || __SILICON_REVISION__ == 0xffff
// Memory range 0x0001FFA0 to 0x0001FFFF reserved for emulator fix for TS201
// silicon anomaly
    mem0_Program    { TYPE(RAM) START(0x00000000) END(0x0001FF9F) WIDTH(32) }
#else
    mem0_Program    { TYPE(RAM) START(0x00000000) END(0x0001FFFF) WIDTH(32) }
#endif
    mem2_DataA      { TYPE(RAM) START(0x00040000) END(0x0004FFFF) WIDTH(32) }
    mem2_DataB      { TYPE(RAM) START(0x00050000) END(0x0005FFFF) WIDTH(32) }
    mem4_DataA      { TYPE(RAM) START(0x00080000) END(0x0008FFFF) WIDTH(32) }

    mem4_IVTIMER0L  { TYPE(RAM) START(0x00090000) LENGTH(1) WIDTH(32) }
    mem4_IVTIMER1L  { TYPE(RAM) START(0x00090001) LENGTH(1) WIDTH(32) }
    mem4_IVLINK0    { TYPE(RAM) START(0x00090002) LENGTH(1) WIDTH(32) }
    mem4_IVLINK1    { TYPE(RAM) START(0x00090003) LENGTH(1) WIDTH(32) }
    mem4_IVLINK2    { TYPE(RAM) START(0x00090004) LENGTH(1) WIDTH(32) }
    mem4_IVLINK3    { TYPE(RAM) START(0x00090005) LENGTH(1) WIDTH(32) }
    mem4_IVDMA0     { TYPE(RAM) START(0x00090006) LENGTH(1) WIDTH(32) }
    mem4_IVDMA1     { TYPE(RAM) START(0x00090007) LENGTH(1) WIDTH(32) }
    mem4_IVDMA2     { TYPE(RAM) START(0x00090008) LENGTH(1) WIDTH(32) }
    mem4_IVDMA3     { TYPE(RAM) START(0x00090009) LENGTH(1) WIDTH(32) }
    mem4_IVDMA4     { TYPE(RAM) START(0x0009000a) LENGTH(1) WIDTH(32) }
    mem4_IVDMA5     { TYPE(RAM) START(0x0009000b) LENGTH(1) WIDTH(32) }
    mem4_IVDMA6     { TYPE(RAM) START(0x0009000c) LENGTH(1) WIDTH(32) }
    mem4_IVDMA7     { TYPE(RAM) START(0x0009000d) LENGTH(1) WIDTH(32) }
    mem4_IVDMA8     { TYPE(RAM) START(0x0009000e) LENGTH(1) WIDTH(32) }
    mem4_IVDMA9     { TYPE(RAM) START(0x0009000f) LENGTH(1) WIDTH(32) }
    mem4_IVDMA10    { TYPE(RAM) START(0x00090010) LENGTH(1) WIDTH(32) }
    mem4_IVDMA11    { TYPE(RAM) START(0x00090011) LENGTH(1) WIDTH(32) }
    mem4_IVDMA12    { TYPE(RAM) START(0x00090012) LENGTH(1) WIDTH(32) }
    mem4_IVDMA13    { TYPE(RAM) START(0x00090013) LENGTH(1) WIDTH(32) }
    mem4_IVIRQ0     { TYPE(RAM) START(0x00090015) LENGTH(1) WIDTH(32) }
    mem4_IVIRQ1     { TYPE(RAM) START(0x00090016) LENGTH(1) WIDTH(32) }
    mem4_IVIRQ2     { TYPE(RAM) START(0x00090017) LENGTH(1) WIDTH(32) }
    mem4_IVIRQ3     { TYPE(RAM) START(0x00090018) LENGTH(1) WIDTH(32) }
    mem4_VIRPT      { TYPE(RAM) START(0x00090019) LENGTH(1) WIDTH(32) }
    mem4_IVBUSLOCK  { TYPE(RAM) START(0x0009001a) LENGTH(1) WIDTH(32) }
    mem4_IVTIMER0H  { TYPE(RAM) START(0x0009001b) LENGTH(1) WIDTH(32) }
    mem4_IVTIMER1H  { TYPE(RAM) START(0x0009001c) LENGTH(1) WIDTH(32) }
    mem4_IVHWERR    { TYPE(RAM) START(0x0009001d) LENGTH(1) WIDTH(32) }

    mem4_DataB      { TYPE(RAM) START(0x00090020) END(0x00092FFF) WIDTH(32) }
    mem4_Heap       { TYPE(RAM) START(0x00093000) END(0x0009EFFF) WIDTH(32) }
    mem4_Stack      { TYPE(RAM) START(0x0009F000) END(0x0009FFFF) WIDTH(32) }
    mem6_DataA      { TYPE(RAM) START(0x000C0000) END(0x000CFFFF) WIDTH(32) }
    mem6_DataB      { TYPE(RAM) START(0x000D0000) END(0x000DAFFF) WIDTH(32) }
    mem6_Heap       { TYPE(RAM) START(0x000DB000) END(0x000DEFFF) WIDTH(32) }
    mem6_Stack      { TYPE(RAM) START(0x000DF000) END(0x000DFFFF) WIDTH(32) }
    mem8_DataA      { TYPE(RAM) START(0x00100000) END(0x0010FFFF) WIDTH(32) }
    mem8_DataB      { TYPE(RAM) START(0x00110000) END(0x0011FFFF) WIDTH(32) }
    mem10_DataA     { TYPE(RAM) START(0x00140000) END(0x0014FFFF) WIDTH(32) }
    mem10_DataB     { TYPE(RAM) START(0x00150000) END(0x0015FFFF) WIDTH(32) }

    MS0             { TYPE(RAM) START(0x30000000) END(0x37FFFFFF) WIDTH(32) }
    MS1             { TYPE(RAM) START(0x38000000) END(0x3FFFFFFF) WIDTH(32) }
    MSSD0           { TYPE(RAM) START(0x40000000) END(0x43FFFFFF) WIDTH(32) }
    MSSD1           { TYPE(RAM) START(0x50000000) END(0x53FFFFFF) WIDTH(32) }
    MSSD2           { TYPE(RAM) START(0x60000000) END(0x63FFFFFF) WIDTH(32) }
    MSSD3           { TYPE(RAM) START(0x70000000) END(0x73FFFFFF) WIDTH(32) }

// Memory blocks need to be less than 2 Gig.
    HOST            { TYPE(RAM) START(0x80000000) END(0x8FFFFFFF) WIDTH(32) }
    HOST1           { TYPE(RAM) START(0x90000000) END(0xAFFFFFFF) WIDTH(32) }
    HOST2           { TYPE(RAM) START(0xB0000000) END(0xCFFFFFFF) WIDTH(32) }
    HOST3           { TYPE(RAM) START(0xD0000000) END(0xEFFFFFFF) WIDTH(32) }
    HOST4           { TYPE(RAM) START(0xF0000000) END(0xFFFFFFFF) WIDTH(32) }
  }

  SECTIONS
  {
    sec_INT_TIMER0L { INPUT_SECTIONS( $OBJS(seg_INT_TIMER0L_64)  $LIBS(seg_INT_TIMER0L_64) ) } > mem4_IVTIMER0L
    sec_INT_TIMER1L { INPUT_SECTIONS( $OBJS(seg_INT_TIMER1L_64)  $LIBS(seg_INT_TIMER1L_64) ) } > mem4_IVTIMER1L
    sec_INT_LINK0   { INPUT_SECTIONS( $OBJS(seg_INT_LINK0_64)  $LIBS(seg_INT_LINK0_64) ) } > mem4_IVLINK0
    sec_INT_LINK1   { INPUT_SECTIONS( $OBJS(seg_INT_LINK1_64)  $LIBS(seg_INT_LINK1_64) ) } > mem4_IVLINK1
    sec_INT_LINK2   { INPUT_SECTIONS( $OBJS(seg_INT_LINK2_64)  $LIBS(seg_INT_LINK2_64) ) } > mem4_IVLINK2
    sec_INT_LINK3   { INPUT_SECTIONS( $OBJS(seg_INT_LINK3_64)  $LIBS(seg_INT_LINK3_64) ) } > mem4_IVLINK3
    sec_INT_DMA0    { INPUT_SECTIONS( $OBJS(seg_INT_DMA0_64)  $LIBS(seg_INT_DMA0_64) ) } > mem4_IVDMA0
    sec_INT_DMA1    { INPUT_SECTIONS( $OBJS(seg_INT_DMA1_64)  $LIBS(seg_INT_DMA1_64) ) } > mem4_IVDMA1
    sec_INT_DMA2    { INPUT_SECTIONS( $OBJS(seg_INT_DMA2_64)  $LIBS(seg_INT_DMA2_64) ) } > mem4_IVDMA2
    sec_INT_DMA3    { INPUT_SECTIONS( $OBJS(seg_INT_DMA3_64)  $LIBS(seg_INT_DMA3_64) ) } > mem4_IVDMA3
    sec_INT_DMA4    { INPUT_SECTIONS( $OBJS(seg_INT_DMA4_64)  $LIBS(seg_INT_DMA4_64) ) } > mem4_IVDMA4
    sec_INT_DMA5    { INPUT_SECTIONS( $OBJS(seg_INT_DMA5_64)  $LIBS(seg_INT_DMA5_64) ) } > mem4_IVDMA5