linsci.c

BCM 控制demo源代码

    
    
    LIN_SCICR2 = LIN_SCICR2_TE | LIN_SCICR2_RE;  	/* enable transmitter & receiver and disable all SCI interrupts */

#if defined (MASTER)
    LIN_SCISR2 |= LIN_SCISR2_BRK13;
#endif /* defined (MASTER) */

#if defined(SCI0)
/* Configure interrupt controller to give different priority */	
	LIN_INT_CFADDR = LIN_INT_CFADDR_IntChan_D;	/* Select page containing SCI0 channel vectors */
#if defined(USEXGATE)	
	LIN_INT_CFDATA3 = (LIN_CfgConst.LIN_SCIIntPriority | LIN_INT_CFADDR_UseXGate);	/* Configure SCI priority */
#else
	LIN_INT_CFDATA3 = LIN_CfgConst.LIN_SCIIntPriority;	/* Configure SCI priority */
#endif /* defined(USEXGATE) */


#elif defined(SCI1)
/* Configure interrupt controller to give different priority */	
	LIN_INT_CFADDR = LIN_INT_CFADDR_IntChan_D;	/* Select page containing SCI1 channel vectors */
#if defined(USEXGATE)	
	LIN_INT_CFDATA2 = (LIN_CfgConst.LIN_SCIIntPriority | LIN_INT_CFADDR_UseXGate);	/* Configure SCI priority */
#else
	LIN_INT_CFDATA2 = LIN_CfgConst.LIN_SCIIntPriority;	/* Configure SCI priority */
#endif /* defined(USEXGATE) */


#elif defined(SCI2)
/* Configure interrupt controller to give different priority */	
	LIN_INT_CFADDR = LIN_INT_CFADDR_IntChan_8;	/* Select page containing SCI2 channel vectors */
#if defined(USEXGATE)	
	LIN_INT_CFDATA5 = (LIN_CfgConst.LIN_SCIIntPriority | LIN_INT_CFADDR_UseXGate);	/* Configure SCI priority */
#else
	LIN_INT_CFDATA5 = LIN_CfgConst.LIN_SCIIntPriority;	/* Configure SCI priority */
#endif /* defined(USEXGATE) */


#elif defined(SCI3)
/* Configure interrupt controller to give different priority */	
	LIN_INT_CFADDR = LIN_INT_CFADDR_IntChan_8;	/* Select page containing SCI3 channel vectors */
#if defined(USEXGATE)	
	LIN_INT_CFDATA4 = (LIN_CfgConst.LIN_SCIIntPriority | LIN_INT_CFADDR_UseXGate);	/* Configure SCI priority */
#else
	LIN_INT_CFDATA4 = LIN_CfgConst.LIN_SCIIntPriority;	/* Configure SCI priority */
#endif /* defined(USEXGATE) */


#elif defined(SCI4)
/* Configure interrupt controller to give different priority */	
	LIN_INT_CFADDR = LIN_INT_CFADDR_IntChan_8;	/* Select page containing SCI4 channel vectors */
#if defined(USEXGATE)	
	LIN_INT_CFDATA3 = (LIN_CfgConst.LIN_SCIIntPriority | LIN_INT_CFADDR_UseXGate);	/* Configure SCI priority */
#else
	LIN_INT_CFDATA3 = LIN_CfgConst.LIN_SCIIntPriority;	/* Configure SCI priority */
#endif /* defined(USEXGATE) */


#elif defined(SCI5)
/* Configure interrupt controller to give different priority */	
	LIN_INT_CFADDR = LIN_INT_CFADDR_IntChan_8;	/* Select page containing SCI5 channel vectors */
#if defined(USEXGATE)	
	LIN_INT_CFDATA2 = (LIN_CfgConst.LIN_SCIIntPriority | LIN_INT_CFADDR_UseXGate);	/* Configure SCI priority */
#else
	LIN_INT_CFDATA2 = LIN_CfgConst.LIN_SCIIntPriority;	/* Configure SCI priority */
#endif /* defined(USEXGATE) */

#elif defined(SCI6)
/* Configure interrupt controller to give different priority */	
	LIN_INT_CFADDR = LIN_INT_CFADDR_IntChan_C;	/* Select page containing SCI4 channel vectors */
#if defined(USEXGATE)	
	LIN_INT_CFDATA1 = (LIN_CfgConst.LIN_SCIIntPriority | LIN_INT_CFADDR_UseXGate);	/* Configure SCI priority */
#else
	LIN_INT_CFDATA1 = LIN_CfgConst.LIN_SCIIntPriority;	/* Configure SCI priority */
#endif /* defined(USEXGATE) */


#elif defined(SCI7)
/* Configure interrupt controller to give different priority */	
	LIN_INT_CFADDR = LIN_INT_CFADDR_IntChan_5;	/* Select page containing SCI5 channel vectors */
#if defined(USEXGATE)	
	LIN_INT_CFDATA3 = (LIN_CfgConst.LIN_SCIIntPriority | LIN_INT_CFADDR_UseXGate);	/* Configure SCI priority */
#else
	LIN_INT_CFDATA3 = LIN_CfgConst.LIN_SCIIntPriority;	/* Configure SCI priority */
#endif /* defined(USEXGATE) */
#endif /* defined(SCI0) */

		
	LIN_TmpSCIStatus = LIN_SCISR1;	/* clear SCI status */
	LIN_TmpSCIByte = LIN_SCIDRL;	
	
	LIN_SCICR2 |= LIN_SCICR2_RIE;    	/* enable RX complited interrupt */
}

#endif  /* !defined(LINAPI_1_0) */


/***************************************************************************
 * Function :   LIN_SCISetBaudRate
 *
 * Description: Programm SCI to particular baud rate
 *
 * Returns:     none
 *
 * Notes:       -   HC12
 *              -   To disable SCI write 0  to SC0BDH and SC0BDL
 *
 **************************************************************************/
void near LIN_SCISetBaudRate( LIN_WORD baudRate )
{
	/* set the baud rate divider  */
	LIN_SCIBDH = (LIN_BYTE)((baudRate >> 8) & 0x001f); 	
	LIN_SCIBDL = (LIN_BYTE)(baudRate & 0x00ff);
}

/****************************************************************************/
/****************************************************************************/
/***                     Interrupt Driven Routins                         ***/
/****************************************************************************/
/****************************************************************************/

/***************************************************************************
 * Function :   LIN_ISR_SCI_Interrupt / l_ifc_rx_sci0 (l_ifc_tx_sci0)
 *
 * Description: SCI interrupt
 *              
 * Returns:     none
 *
 * Notes:       
 *              Freescale API -- direct ISR.
 *              LIN API      -- LIN API function --
 *                  l_ifc_rx_sci0 and l_ifc_tx_sci0 also becouse
 *
 *              SCI interrupts:
 *                 RX completed interrupt          enabled forever
 *                 TX enable interrupt             disabled forever
 *                 TX completed interrupt          enabled only while: 
 *                                                 - break symbol send 
 *                                                 - wakeup symbol send 
 *                                                 disabled after processing
 *                 Overrun interrupt               enabled but not processed
 *                                                 and only cleared
 *
 **************************************************************************/
#if defined(LINAPI_1_0)
void l_ifc_rx_sci0( void )
#else /* defined(LINAPI_1_0) */
LIN_INTERRUPT LIN_ISR_SCI_Interrupt ( void )
#endif /* defined(LINAPI_1_0) */
{
#if !defined (USEXGATE)

    LIN_DBG_SET_PORT_0;

#if defined(LINAPI_1_0)
    if ( (LIN_StateFlags & LIN_FLAG_DISCONNECT) == 0 )
    {   
        /* work only if SCI connected */
#endif /* defined(LINAPI_1_0) */

	LIN_TmpSCIStatus = LIN_SCISR1;	/* clear SCI status */
	LIN_TmpSCIByte   = LIN_SCIDRL;	

	if ( LIN_TmpSCIStatus & LIN_SCISR1_RDRF )	
        {   
		if ( LIN_TmpSCIStatus & LIN_SCISR1_FE )	
            {   /********************************************************* error interrupt */
                /* only frame error was processed */

			if ( LIN_TmpSCIByte == 0  )	/* check whether a LIN  bit break has been recieved*/
                {                        
                    LIN_DBG_SET_PORT_5;         /* indicate break symbol recognized  */

                    LIN_FrameError(LIN_NORMALBREAK);  

                    LIN_DBG_CLR_PORT_5;
                }
                else
                {
				    LIN_SCICR2 &= ~LIN_SCICR2_RE;    	/* NB: disable and enable SCI to prevent */
										/*     distinction next zero level bit as start bit */
                    
                    LIN_DBG_SET_PORT_3;             /* indicate frame error recognized */

                    LIN_FrameError(LIN_FRAMEERROR);

                    LIN_DBG_CLR_PORT_3;

				    LIN_SCICR2 |= LIN_SCICR2_RE;	/* enable SCI Rx */
                }
            }   /****************************************************** end error interrupt */    

            else
            {  /******************************************************** receiver interrupt */
                LIN_DBG_SET_PORT_1;

                LIN_RxCompleted();

                LIN_DBG_CLR_PORT_1;
            }  /**************************************************** end receiver interrupt */
        }
        else 
        {      /***************************************************** transmitter interrupt */ 
		LIN_SCICR2  &= ~( LIN_SCICR2_TCIE );	/* Disable Tx completed */
												/* interrupt we cann憈 clear it */
            
 
		if ( LIN_TmpSCIStatus & LIN_SCISR1_TC )	
	
            {  /**************************************************** tx completed interrupt */
#if defined(SLAVE)
                LIN_DBG_SET_PORT_2;

                LIN_TxCompleted();

                /* if Rx interrupt for break occures after Tx interrupt
                   we ignore it in LIN_RxCompleted function */

                LIN_DBG_CLR_PORT_2;
#endif /* defined(SLAVE) */
#if defined(MASTER)
#if defined(LIN_DBG_CHECK_INTERNAL_ERROR)
                LIN_InternalError = LIN_ERROR_8;
                while (1)
                {}
#endif /* defined(LIN_DBG_CHECK_INTERNAL_ERROR) */
#endif /* defined(MASTER) */
           }

#if defined(LIN_DBG_CHECK_INTERNAL_ERROR)
            else
            {  /****************************** Overrun, TX enable  interrupt not processed */
                LIN_InternalError = LIN_ERROR_8;
                while (1)
                {}
            }
#endif /* defined(LIN_DBG_CHECK_INTERNAL_ERROR) */
        }

#if defined(LINAPI_1_0)
    }
#endif /* defined(LINAPI_1_0) */

    LIN_DBG_CLR_PORT_0;
#else
#if defined(SCI0)
	LIN_XGIF6 = LIN_XGIF_ICh6B;	/* SCI0 clear interrupt flag */
#elif defined(SCI1)
	LIN_XGIF6 = LIN_XGIF_ICh6A;	/* SCI1 clear interrupt flag */
#elif defined(SCI2)
	LIN_XGIF4 = LIN_XGIF_ICh45;	/* SCI2 clear interrupt flag */
#elif defined(SCI3)
	LIN_XGIF4 = LIN_XGIF_ICh44;	/* SCI3 clear interrupt flag */
#elif defined(SCI4)
	LIN_XGIF4 = LIN_XGIF_ICh43;	/* SCI4 clear interrupt flag */
#elif defined(SCI5)
	LIN_XGIF4 = LIN_XGIF_ICh42;	/* SCI5 clear interrupt flag */
#elif defined(SCI6)
	LIN_XGIF6 = LIN_XGIF_ICh61;	/* SCI5 clear interrupt flag */
#elif defined(SCI7)
	LIN_XGIF2 = LIN_XGIF_ICh2B;	/* SCI5 clear interrupt flag */		
#endif /* defined(SCI0) */ 
    LIN_Command();
#endif /* !defined (USEXGATE) */

}

#pragma CODE_SEG DEFAULT