linsci.cxgate

BCM 控制demo源代码

#define LINSCI_CXGATE
/******************************************************************************
*                                                       
*       Copyright (C) 2005 Freescale Semiconductor, Inc.
*       All Rights Reserved								              
*														                            
* Filename:     linsci.cxgate
*														                            
* Revision:      										                    
*														                            
* Functions:    SCI interrupt
*												                            
* Description:
*												                            
* Notes:        
*												                            
******************************************************************************/

#include <hidef.h>      /* common defines and macros */
#include <linxgate.h>
#include <linbase.h>

/******************************************************************************
* VARIABLE DEFINITIONS 
******************************************************************************/

/* This wariable reflect the state of LIN physical layer during LIN colision detection:
   - 0 -> OK
   - 1 -> RxD pin low, i.e. LIN signal wire connected to GND, 
   - 2 -> RxD pin high, i.e. LIN signal wire connected to Vsup */ 
extern unsigned char failLIN = 0;


#if defined	(USEXGATE)
/****************************************************************************
 * All common-purpose RAM variables shall be declared here.
 ***************************************************************************/
extern LIN_ZPAGE LIN_BYTE  LIN_TmpSCIStatus;

/****************************************************************************
 * Functions 
 ***************************************************************************/

/****************************************************************************/
/****************************************************************************/
/***                     Interrupt Driven Routins                         ***/
/****************************************************************************/
/****************************************************************************/

/***************************************************************************
 * Function :   LIN_ISR_SCI_Interrupt / l_ifc_rx_sci0 (l_ifc_tx_sci0)
 *
 * Description: SCI interrupt
 *              
 * Returns:     none
 *
 * Notes:       
 *              Freescale API -- direct ISR.
 *              LIN API      -- LIN API function --
 *                  l_ifc_rx_sci0 and l_ifc_tx_sci0 also becouse
 *
 *              SCI interrupts:
 *                 RX completed interrupt          enabled forever
 *                 TX enable interrupt             disabled forever
 *                 TX completed interrupt          enabled only while: 
 *                                                 - break symbol send 
 *                                                 - wakeup symbol send 
 *                                                 disabled after processing
 *                 Overrun interrupt               enabled but not processed
 *                                                 and only cleared
 *
 **************************************************************************/
#if defined(LINAPI_1_0)
void l_ifc_rx_sci0( void )
#else /* defined(LINAPI_1_0) */
void interrupt XLIN_ISR_SCI_Interrupt ( void )
#endif /* defined(LINAPI_1_0) */
{
    LIN_DBG_SET_PORT_0;

#if defined(LINAPI_1_0)
    if ( (LIN_StateFlags & LIN_FLAG_DISCONNECT) == 0 )
    {   
        /* work only if SCI connected */
#endif /* defined(LINAPI_1_0) */


    /* LIN colision detect, add by rc574c on 19-Jan-2006 */
    /* Alternative control registers are sharing 
	   the address space: module base + (0x0000 -> 0x0002) */ 
	SCISR2 |= 0x80;
	
    /* Bit error occured ? */
    if (SCIASR1 & 0x02)
    {
        /* Clear Bit error flag */
        SCIASR1 |= 0x02; 
        
        /* Read value of SCI RxD pin and increment:
           - 1 -> low, i.e. LIN signal wire connected to GND, 
           - 2 -> high, i.e. LIN signal wire connected to Vsup */ 
        failLIN = (((SCIASR1 & 0x04) >> 2) & 0x01) + 1;
        
        /* SCIBDH, SCIBDL and SCICR1 registers are sharing 
	       the address space: module base + (0x0000 -> 0x0002) */
        SCISR2 &= 0x7F;    
 
    	return;
    }
    else
    {
        /* Reset label, none colision occured */
		failLIN = 0;

		/* SCIBDH, SCIBDL and SCICR1 registers are sharing 
		   the address space: module base + (0x0000 -> 0x0002) */ 
		SCISR2 &= 0x7F;        
    }
    

	LIN_TmpSCIStatus = LIN_SCISR1;	/* clear SCI status */
	LIN_TmpSCIByte = LIN_SCIDRL;	

	if ( LIN_TmpSCIStatus & LIN_SCISR1_RDRF )	
        {   
		if ( LIN_TmpSCIStatus & LIN_SCISR1_FE )	
            {   /********************************************************* error interrupt */
                /* only frame error was processed */
			if ( LIN_TmpSCIByte == 0  )	/* check whether a LIN  bit break has been recieved*/
                {                        
                    LIN_DBG_SET_PORT_5;         /* indicate break symbol recognized  */

                    XLIN_FrameError(LIN_NORMALBREAK);  

                    LIN_DBG_CLR_PORT_5;
                }
                else
                {
	    			LIN_SCICR2 &= ~LIN_SCICR2_RE;    	/* NB: disable and enable SCI to prevent */
		                								/*     distinction next zero level bit as start bit */
                    
                    LIN_DBG_SET_PORT_3;             /* indicate frame error recognized */

                    XLIN_FrameError(LIN_FRAMEERROR);

                    LIN_DBG_CLR_PORT_3;

    				LIN_SCICR2 |= LIN_SCICR2_RE;	/* enable SCI Rx */
                }
            }   /****************************************************** end error interrupt */    

            else
            {  /******************************************************** receiver interrupt */
                LIN_DBG_SET_PORT_1;

                XLIN_RxCompleted();

                LIN_DBG_CLR_PORT_1;
            }  /**************************************************** end receiver interrupt */
        }

        else 
        {      /***************************************************** transmitter interrupt */ 
		LIN_SCICR2  &= ~( LIN_SCICR2_TCIE );	/* Disable Tx completed */
												/* interrupt we cann憈 clear it */
            
 
		if ( LIN_TmpSCIStatus & LIN_SCISR1_TC )	
	
            {  /**************************************************** tx completed interrupt */
#if defined(SLAVE)
                LIN_DBG_SET_PORT_2;

                XLIN_TxCompleted();

                /* if Rx interrupt for break occures after Tx interrupt
                   we ignore it in LIN_RxCompleted function */

                LIN_DBG_CLR_PORT_2;
#endif /* defined(SLAVE) */
#if defined(MASTER)
#if defined(LIN_DBG_CHECK_INTERNAL_ERROR)
                LIN_InternalError = LIN_ERROR_8;
                while (1)
                {}
#endif /* defined(LIN_DBG_CHECK_INTERNAL_ERROR) */
#endif /* defined(MASTER) */
            }

    #if defined(LIN_DBG_CHECK_INTERNAL_ERROR)
       else
            {  /****************************** Overrun, TX enable  interrupt not processed */
                LIN_InternalError = LIN_ERROR_8;
                while (1)
                {}
            }
    #endif /* defined(LIN_DBG_CHECK_INTERNAL_ERROR) */
        }

#if defined(LINAPI_1_0)
    }
#endif /* defined(LINAPI_1_0) */

    LIN_DBG_CLR_PORT_0;
}

#endif /* defined USEXGATE) */