class.ptf

altera 公司内部PWM的HDL及驱动代码

                  EDIT e2
                  {
                     id = "duty_cycle_reg_init";
                     editable = "1";
                     title = "duty_cycle_reg_init:";
                     columns = "40";
                     tooltip = "default value: 32'b00000000000000000000000000000000";
                     DATA 
                     {
                        $H/duty_cycle_reg_init = "$";
                     }
                     q = "'";
                     warning = "{{ if(!(regexp('ugly_'+$H/duty_cycle_reg_init,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/duty_cycle_reg_init,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/duty_cycle_reg_init,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/duty_cycle_reg_init,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/duty_cycle_reg_init,'ugly_-?[0-9]+')))'duty_cycle_reg_init must be numeric constant, not '+$H/duty_cycle_reg_init; }}";
                  }
               }
            }
         }
      }
   }
   SOPC_Builder_Version = "5.10";
   COMPONENT_BUILDER 
   {
      HDL_PARAMETERS 
      {
         # generated by CBDocument.getParameterContainer
         # used only by Component Editor
         HDL_PARAMETER clock_divide_reg_init
         {
            parameter_name = "clock_divide_reg_init";
            type = "integer";
            default_value = "32'b00000000000000000000000000000000";
            editable = "1";
            tooltip = "";
         }
         HDL_PARAMETER duty_cycle_reg_init
         {
            parameter_name = "duty_cycle_reg_init";
            type = "integer";
            default_value = "32'b00000000000000000000000000000000";
            editable = "1";
            tooltip = "";
         }
      }
      SW_FILES 
      {
         FILE 
         {
            filepath = "HAL/inc/altera_avalon_pwm_routines.h";
            type = "HAL (HAL/inc/)";
         }
         FILE 
         {
            filepath = "inc/altera_avalon_pwm_regs.h";
            type = "Registers (inc/)";
         }
         FILE 
         {
            filepath = "HAL/src/altera_avalon_pwm_routines.c";
            type = "HAL (HAL/src/)";
         }
      }
      built_on = "2006.06.05.16:17:32";
      CACHED_HDL_INFO 
      {
         # cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection
         # used only by Component Builder
         FILE pwm_avalon_interface.v
         {
            file_mod = "Fri Jan 14 17:55:44 CST 2005";
            quartus_map_start = "Mon Jun 05 16:13:08 CST 2006";
            quartus_map_finished = "Mon Jun 05 16:13:25 CST 2006";
            #found 1 valid modules
            WRAPPER pwm_avalon_interface
            {
               CLASS pwm_avalon_interface
               {
                  CB_GENERATOR 
                  {
                     HDL_FILES 
                     {
                        FILE 
                        {
                           use_in_simulation = "1";
                           use_in_synthesis = "1";
                           filepath = "D:/开发设计/altera/pwm_source/pwm_hw/pwm_avalon_interface.v";
                        }
                     }
                     top_module_name = "pwm_avalon_interface";
                     emit_system_h = "0";
                  }
                  MODULE_DEFAULTS global_signals
                  {
                     class = "pwm_avalon_interface";
                     class_version = "1.0";
                     SYSTEM_BUILDER_INFO 
                     {
                        Instantiate_In_System_Module = "1";
                     }
                     SLAVE avalon_slave_0
                     {
                        SYSTEM_BUILDER_INFO 
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING 
                        {
                           PORT resetn
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT avalon_chip_select
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT address
                           {
                              width = "2";
                              width_expression = "";
                              direction = "input";
                              type = "address";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT write
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "write";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT write_data
                           {
                              width = "32";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT read
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "read";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT read_data
                           {
                              width = "32";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT pwm_out
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                        }
                     }
                     PORT_WIRING 
                     {
                        PORT clk
                        {
                           width = "1";
                           width_expression = "";
                           direction = "input";
                           type = "clk";
                           is_shared = "0";
                           vhdl_record_name = "";
                           vhdl_record_type = "";
                        }
                     }
                  }
                  USER_INTERFACE 
                  {
                     USER_LABELS 
                     {
                        name = "pwm_avalon_interface";
                        technology = "imported components";
                     }
                  }
                  SOPC_Builder_Version = "0.0";
                  COMPONENT_BUILDER 
                  {
                     HDL_PARAMETERS 
                     {
                        # generated by CBDocument.getParameterContainer
                        # used only by Component Editor
                        HDL_PARAMETER clock_divide_reg_init
                        {
                           parameter_name = "clock_divide_reg_init";
                           type = "integer";
                           default_value = "32'b00000000000000000000000000000000";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER duty_cycle_reg_init
                        {
                           parameter_name = "duty_cycle_reg_init";
                           type = "integer";
                           default_value = "32'b00000000000000000000000000000000";
                           editable = "1";
                           tooltip = "";
                        }
                     }
                  }
               }
            }
         }
         FILE pwm_register_file.v
         {
            file_mod = "Thu Jan 13 17:00:10 CST 2005";
            quartus_map_start = "Mon Jun 05 16:13:30 CST 2006";
            quartus_map_finished = "Mon Jun 05 16:13:38 CST 2006";
            #found 1 valid modules
            WRAPPER pwm_register_file
            {
               CLASS pwm_register_file
               {
                  CB_GENERATOR 
                  {
                     HDL_FILES 
                     {
                        FILE 
                        {
                           use_in_simulation = "1";
                           use_in_synthesis = "1";
                           filepath = "D:/开发设计/altera/pwm_source/pwm_hw/pwm_register_file.v";
                        }
                     }
                     top_module_name = "pwm_register_file";
                     emit_system_h = "0";
                  }
                  MODULE_DEFAULTS global_signals
                  {
                     class = "pwm_register_file";
                     class_version = "1.0";
                     SYSTEM_BUILDER_INFO 
                     {
                        Instantiate_In_System_Module = "1";
                     }
                     SLAVE avalon_slave_0
                     {
                        SYSTEM_BUILDER_INFO 
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING 
                        {
                           PORT resetn