xor2.vhd

来自「两输入异或门 两输入异或门」· VHDL 代码 · 共 12 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY XOR2 IS
  PORT(A,B:IN STD_LOGIC;
     Y:OUT STD_LOGIC);
END ENTITY XOR2;
ARCHITECTURE ONE OF XOR2 IS
  BEGIN
  Y<=(NOT A AND B) OR ( NOT B AND A);
END ARCHITECTURE ONE;