v_regler.mdl

电机的PID控制

		Cell			"GenerateTestInterfaces"
		Cell			"MultiInstanceERTCode"
		Cell			"PurelyIntegerCode"
		Cell			"SupportNonFinite"
		Cell			"SupportComplex"
		Cell			"SupportAbsoluteTime"
		Cell			"SupportContinuousTime"
		Cell			"SupportNonInlinedSFcns"
		PropName		"DisabledProps"
	      }
	      Version		      "1.2.0"
	      TargetFcnLib	      "ansi_tfl_tmw.mat"
	      TargetLibSuffix	      ""
	      TargetPreCompLibLocation ""
	      GenFloatMathFcnCalls    "ANSI_C"
	      UtilityFuncGeneration   "Auto"
	      GenerateFullHeader      on
	      GenerateSampleERTMain   off
	      GenerateTestInterfaces  off
	      IsPILTarget	      off
	      ModelReferenceCompliant on
	      IncludeMdlTerminateFcn  on
	      CombineOutputUpdateFcns off
	      SuppressErrorStatus     off
	      IncludeERTFirstTime     on
	      ERTFirstTimeCompliant   off
	      IncludeFileDelimiter    "Auto"
	      ERTCustomFileBanners    off
	      SupportAbsoluteTime     on
	      LogVarNameModifier      "rt_"
	      MatFileLogging	      on
	      MultiInstanceERTCode    off
	      SupportNonFinite	      on
	      SupportComplex	      on
	      PurelyIntegerCode	      off
	      SupportContinuousTime   on
	      SupportNonInlinedSFcns  on
	      ExtMode		      off
	      ExtModeStaticAlloc      off
	      ExtModeTesting	      off
	      ExtModeStaticAllocSize  1000000
	      ExtModeTransport	      0
	      ExtModeMexFile	      "ext_comm"
	      RTWCAPISignals	      off
	      RTWCAPIParams	      off
	      RTWCAPIStates	      off
	      GenerateASAP2	      off
	    }
	    PropName		    "Components"
	  }
	}
	PropName		"Components"
      }
      Name		      "Configuration"
      SimulationMode	      "normal"
      CurrentDlgPage	      "Solver"
    }
    PropName		    "ConfigurationSets"
  }
  Simulink.ConfigSet {
    $PropName		    "ActiveConfigurationSet"
    $ObjectID		    1
  }
  BlockDefaults {
    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "Arial"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
  }
  BlockParameterDefaults {
    Block {
      BlockType		      Gain
      Gain		      "1"
      Multiplication	      "Element-wise(K.*u)"
      ParameterDataTypeMode   "Same as input"
      ParameterDataType	      "sfix(16)"
      ParameterScalingMode    "Best Precision: Matrix-wise"
      ParameterScaling	      "2^0"
      OutDataTypeMode	      "Same as input"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      LockScale		      off
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Inport
      Port		      "1"
      UseBusObject	      off
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      LatchByDelayingOutsideSignal off
      LatchByCopyingInsideSignal off
      Interpolate	      on
    }
    Block {
      BlockType		      Integrator
      ExternalReset	      "none"
      InitialConditionSource  "internal"
      InitialCondition	      "0"
      LimitOutput	      off
      UpperSaturationLimit    "inf"
      LowerSaturationLimit    "-inf"
      ShowSaturationPort      off
      ShowStatePort	      off
      AbsoluteTolerance	      "auto"
      IgnoreLimit	      off
      ZeroCross		      on
    }
    Block {
      BlockType		      Outport
      Port		      "1"
      UseBusObject	      off
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      OutputWhenDisabled      "held"
      InitialOutput	      "[]"
    }
    Block {
      BlockType		      SubSystem
      ShowPortLabels	      on
      Permissions	      "ReadWrite"
      PermitHierarchicalResolution "All"
      TreatAsAtomicUnit	      off
      SystemSampleTime	      "-1"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
    }
    Block {
      BlockType		      Sum
      IconShape		      "rectangular"
      Inputs		      "++"
      InputSameDT	      on
      OutDataTypeMode	      "Same as first input"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      LockScale		      off
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	on
      SampleTime	      "-1"
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Arial"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "Arial"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "V_Regler"
    Location		    [480, 93, 1060, 386]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "A4"
    PaperUnits		    "centimeters"
    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
    TiledPageScale	    1
    ShowPageBoundaries	    off
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      Inport
      Name		      "V-Ist"
      Position		      [135, 23, 165, 37]
      IconDisplay	      "Port number"
    }
    Block {
      BlockType		      Inport
      Name		      "V-Soll"
      Position		      [135, 53, 165, 67]
      Port		      "2"
      IconDisplay	      "Port number"
    }
    Block {
      BlockType		      SubSystem
      Name		      "Subsystem_V_Regler"
      Ports		      [2, 1]
      Position		      [260, 15, 300, 75]
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      MaskHideContents	      off
      System {
	Name			"Subsystem_V_Regler"
	Location		[490, 98, 930, 297]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"A4"
	PaperUnits		"centimeters"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "V-Ist"
	  Position		  [25, 78, 55, 92]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "V-Soll"
	  Position		  [25, 33, 55, 47]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Gain
	  Name			  "Gain1"
	  Position		  [165, 101, 245, 149]
	  ShowName		  off
	  Gain			  "Kp_V/Tn_V"
	  ParameterDataTypeMode	  "Inherit via internal rule"
	  OutDataTypeMode	  "Inherit via internal rule"
	  SaturateOnIntegerOverflow off
	}
	Block {
	  BlockType		  Integrator
	  Name			  "Int_R"
	  Ports			  [1, 1]
	  Position		  [275, 110, 305, 140]
	  IgnoreLimit		  off
	}
	Block {
	  BlockType		  Gain
	  Name			  "P-Anteil"
	  Position		  [200, 25, 255, 55]
	  Gain			  "Kp_V"
	  ParameterDataTypeMode	  "Inherit via internal rule"
	  OutDataTypeMode	  "Inherit via internal rule"
	  SaturateOnIntegerOverflow off
	}
	Block {
	  BlockType		  Sum
	  Name			  "Sum1"
	  Ports			  [2, 1]
	  Position		  [110, 30, 130, 50]
	  ShowName		  off
	  IconShape		  "round"
	  Inputs		  "|+-"
	  InputSameDT		  off
	  OutDataTypeMode	  "Inherit via internal rule"
	  SaturateOnIntegerOverflow off
	}
	Block {
	  BlockType		  Sum
	  Name			  "Sum2"
	  Ports			  [2, 1]
	  Position		  [315, 30, 335, 50]
	  ShowName		  off
	  IconShape		  "round"
	  Inputs		  "|++"
	  InputSameDT		  off
	  OutDataTypeMode	  "Inherit via internal rule"
	  SaturateOnIntegerOverflow off
	}
	Block {
	  BlockType		  Outport
	  Name			  "I-Soll"
	  Position		  [385, 33, 415, 47]
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Line {
	  SrcBlock		  "V-Soll"
	  SrcPort		  1
	  DstBlock		  "Sum1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "V-Ist"
	  SrcPort		  1
	  Points		  [60, 0]
	  DstBlock		  "Sum1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Sum1"
	  SrcPort		  1
	  Points		  [0, 0; 15, 0]
	  Branch {
	    DstBlock		    "P-Anteil"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "Gain1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Gain1"
	  SrcPort		  1
	  Points		  [0, 0]
	  DstBlock		  "Int_R"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Int_R"
	  SrcPort		  1
	  Points		  [15, 0]
	  DstBlock		  "Sum2"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "P-Anteil"
	  SrcPort		  1
	  Points		  [0, 0]
	  DstBlock		  "Sum2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sum2"
	  SrcPort		  1
	  Points		  [0, 0]
	  DstBlock		  "I-Soll"
	  DstPort		  1
	}
	Annotation {
	  Name			  "I-Anteil"
	  Position		  [232, 174]
	  UseDisplayTextAsClickCallback	off
	}
      }
    }
    Block {
      BlockType		      Outport
      Name		      "I-Soll"
      Position		      [360, 38, 390, 52]
      IconDisplay	      "Port number"
      BusOutputAsStruct	      off
    }
    Line {
      SrcBlock		      "V-Ist"
      SrcPort		      1
      DstBlock		      "Subsystem_V_Regler"
      DstPort		      1
    }
    Line {
      SrcBlock		      "V-Soll"
      SrcPort		      1
      DstBlock		      "Subsystem_V_Regler"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Subsystem_V_Regler"
      SrcPort		      1
      DstBlock		      "I-Soll"
      DstPort		      1
    }
  }
}