📄 gpifburst8a.lst
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234 5 EP2GPIFTCH = EP2BCH; // Setup transaction count
235 5 EP2GPIFTCL = EP2BCL; // Set EP2GPIFTC = EP2BC
236 5 EP2BCL = 0x00; // AUTOOUT=0, so "pass-on" pkt. to master (GPIF)
237 5 // Skip bit is 0 +> pass on packet to master
238 5 // Once master xfr's OUT pkt, it "auto" (re)arms
239 5
240 5 GPIFTRIG = GPIF_EP2; // Trigger FIFO write transaction(s), using SFR
241 5 // R/W=0, EP[1:0]=FIFO_EpNum for EPx write(s)
C51 COMPILER V7.00 GPIFBURST8A 05/20/2003 15:33:07 PAGE 5
242 5 if(xFIFOTC_OUT < 0x0200)// Handle short pkt. to slave, via PA0
243 5 {
244 6 while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
245 6 {
246 7 ledX_rdvar = LED1_ON; // GPIF busy
247 7 }
248 6 SHORTPKT = 0; // Signal SHORTPKT to slave (PA0)
249 6 SHORTPKT = 1;
250 6 }
251 5 else // Was max pkt. size
252 5 {
253 6 }
254 5 }
255 4 else // Handle host sending zero length pkt.
256 4 {
257 5 EP2BCL = 0x80; // AUTOOUT=0, so "skip" zerolen pkt.
258 5 // Manually commit packet to the master
259 5 SHORTPKT = 0; // Signal SHORTPKT to slave (PA0)
260 5 SHORTPKT = 1;
261 5 }
262 4 }
263 3 else // GPIF is busy
264 3 {
265 4 ledX_rdvar = LED1_ON; // GPIF is still busy withthe last transfer
266 4 }
267 3
268 3 }
269 2 else // Host is "not" sending data and the
270 2 { // ...slave has taken all data and
271 3 } // ...nothing in the buffer
272 2
273 2
274 2 // Does the slave have data for us...
275 2 if( GPIFTRIG & 0x80 ) // If GPIF done then check slave status
276 2 {
277 3 ledX_rdvar = LED1_OFF; // GPIF is not busy
278 3 if( in_token_event ) // Set via vendor command 0xE0
279 3 {
280 4 ledX_rdvar = LED0_OFF;
281 4 if( !( EP2468STAT & 0x80 ) )// if EP8F=0, buffer is available
282 4 {
283 5 // Trigger FIFO read transaction(s), using SFR
284 5 // R/W=1, EP[1:0]=FIFO_EpNum for EPx read(s)
285 5 GPIFTRIG = GPIFTRIGRD | GPIF_EP8;
286 5 in_token_event = 0;// Clear event flag
287 5 while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
288 5 {
289 6 ledX_rdvar = LED1_ON; // GPIF busy
290 6 }
291 5 INPKTEND = 0x08; // AUTOIN=0, so 8051 must "pass-on" pkt to host
292 5 // Short packet => commit to hoist by writting endp
293 5 } // ....to the INPKTEND register
294 4 else // If EP busy then host is behind (slow) and we
295 4 { // ...still have two buffers containing data
296 5 }
297 4 }
298 3 else // in_token_event not asserted by vendor request
299 3 {
300 4 }
301 3 }
302 2 else // GPIF is busy
303 2 {
C51 COMPILER V7.00 GPIFBURST8A 05/20/2003 15:33:07 PAGE 6
304 3 ledX_rdvar = LED1_ON; // GPIF is still busy withthe last transfer
305 3 }
306 2 }
307 1 else
308 1 {
309 2 ledX_rdvar = LED0_OFF; // LED0 is OFF: GPIF not triggered in TD_POll
310 2 }
311 1 }
312
313 BOOL TD_Suspend(void) // Called before the device goes into suspend mode
314 {
315 1 return(TRUE);
316 1 }
317
318 BOOL TD_Resume(void) // Called after the device resumes
319 {
320 1 return(TRUE);
321 1 }
322
323 //-----------------------------------------------------------------------------
324 // Device Request hooks
325 // The following hooks are called by the end point 0 device request parser.
326 //-----------------------------------------------------------------------------
327
328 BOOL DR_GetDescriptor(void)
329 {
330 1 return(TRUE);
331 1 }
332
333 BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received
334 {
335 1
336 1 Configuration = SETUPDAT[ 2 ];
337 1 return( TRUE ); // Handled by user code
338 1 }
339
340 BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received
341 {
342 1 EP0BUF[0] = Configuration;
343 1 EP0BCH = 0;
344 1 EP0BCL = 1;
345 1 return(TRUE); // Handled by user code
346 1 }
347
348 BOOL DR_SetInterface(void) // Called when a Set Interface command is received
349 {
350 1 AlternateSetting = SETUPDAT[2];
351 1 return(TRUE); // Handled by user code
352 1 }
353
354 BOOL DR_GetInterface(void) // Called when a Set Interface command is received
355 {
356 1 EP0BUF[0] = AlternateSetting;
357 1 EP0BCH = 0;
358 1 EP0BCL = 1;
359 1 return(TRUE); // Handled by user code
360 1 }
361
362 BOOL DR_GetStatus(void)
363 {
364 1 return(TRUE);
365 1 }
C51 COMPILER V7.00 GPIFBURST8A 05/20/2003 15:33:07 PAGE 7
366
367 BOOL DR_ClearFeature(void)
368 {
369 1 return(TRUE);
370 1 }
371
372 BOOL DR_SetFeature(void)
373 {
374 1 return(TRUE);
375 1 }
376
377
378
379
380 BOOL DR_VendorCmnd( void )
381 {
382 1 switch( SETUPDAT[ 1 ] )
383 1 {
384 2 case VX_A2:
385 2 { // Get status of peripheral function, by doing a GPIF single read transaction
386 3 // using register(s) in XDATA space, dummy read
387 3 while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
388 3 {
389 4 ledX_rdvar = LED1_ON; // GPIF Busy
390 4 }
391 3 *EP0BUF = XGPIFSGLDATLX; // trigger GPIF single byte read transaction
392 3 while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
393 3 {
394 4 ledX_rdvar = LED1_ON; // GPIF busy
395 4 }
396 3 ledX_rdvar = LED1_OFF; // GPIF not busy anymore
397 3 *EP0BUF = XGPIFSGLDATLNOX; // ...GPIF reads byte from PERIPHERAL
398 3 EP0BCH = 0;
399 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
400 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
401 3 BLINK_LED();
402 3 break;
403 3 }
404 2 case VX_A3:
405 2 { // Tell peripheral we're going into HS mode, by doing a GPIF single write transaction
406 3 while( !( GPIFTRIG & 0x80 ) ) // Poll GPIFTRIG.7 Done bit
407 3 {
408 4 ledX_rdvar = LED1_ON; // GPIF busy
409 4 }
410 3 ledX_rdvar = LED1_OFF; // GPIF not busy anymore
411 3 XGPIFSGLDATLX = 0xA3; // Trigger GPIF
412 3 *EP0BUF = 0xA3;
413 3 EP0BCH = 0;
414 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
415 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
416 3 BLINK_LED();
417 3 break;
418 3 }
419 2 case VX_A4:
420 2 { // Abort current GPIF transaction...
421 3 GPIFABORT = 0xFF;
422 3 *EP0BUF = 0xA4;
423 3 EP0BCH = 0;
424 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
425 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
426 3 BLINK_LED();
427 3 break;
C51 COMPILER V7.00 GPIFBURST8A 05/20/2003 15:33:07 PAGE 8
428 3 }
429 2 case VX_A6:
430 2 { // Turn debug LED[3:0] off...
431 3 ledX_rdvar = LED0_OFF;
432 3 ledX_rdvar = LED1_OFF;
433 3 ledX_rdvar = LED2_OFF;
434 3 ledX_rdvar = LED3_OFF;
435 3 *EP0BUF = 0xA6;
436 3 EP0BCH = 0;
437 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
438 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
439 3 BLINK_LED();
440 3 break;
441 3 }
442 2 case VX_A7:
443 2 { // Setup peripheral for high speed FIFO xfr(s), TC=8 bytes
444 3 EP8GPIFTCH = 0x00; // setup transaction count
445 3 EP8GPIFTCL = 0x08; // set EP8GPIFTC = 8
446 3 *EP0BUF = 0xA7;
447 3 EP0BCH = 0;
448 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
449 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
450 3 BLINK_LED();
451 3 break;
452 3 }
453 2 case VX_A8:
454 2 { // Do a FIFO Rd transaction w/TC=8 into EP8
455 3 if( !( EP2468STAT & 0x80 ) )
456 3 { // EP8FF=0, when buffer is available...
457 4 // trigger FIFO read transaction(s), using SFR
458 4 while( !( GPIFTRIG & 0x80 ) ) // Poll GPIFTRIG.7 Done bit
459 4 {
460 5 ledX_rdvar = LED1_ON; // GPIF busy
461 5 }
462 4 ledX_rdvar = LED1_OFF; // GPIF not busy anymore
463 4 GPIFTRIG = GPIFTRIGRD | GPIF_EP8; // R/W=1, EP[1:0]=FIFO_EpNum for EPx read(s)
464 4 *EP0BUF = 0xA8; // return that there was a buffer available
465 4 BLINK_LED();
466 4 }
467 3 else
468 3 { // If EP busy then host is behind...
469 4 *EP0BUF = 0x00; // Buffer space wasn't available and we still have
470 4 // two buffers containing data
471 4 ledX_rdvar = LED3_ON; // Indicate buffer is not available
472 4 }
473 3 EP0BCH = 0;
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