sysinit.s

ARM920T S3C440B 原碼

    
    [ MEMORY_CHECK
    ldr     r4,=SDRAM_BANK1_WRITE
    bl      SEGMENT_DISPLAY
    ldr	    r0,=0x55aaaa55
    ldr     r1,=DRAM1_CHECK_END-4
    ldr     r2,=DRAM1_CHECK_START-4

WRITE_DRAM1
    ADD     R2,R2,#4
    STR	    R0,[R2]
    CMP	    R2,R1
    BNE     WRITE_DRAM1
	
    ldr     r4,=SDRAM_BANK1_READ
    bl      SEGMENT_DISPLAY
    ldr	    r3,=0x55aaaa55
    ldr     r1,=DRAM1_CHECK_END-4
    ldr     r2,=DRAM1_CHECK_START-4

READ_DRAM1
    ADD	    R2,R2,#4
    LDR	    R0,[R2]
    CMP	    R0,R3

    BNE	    DRAM_ERROR
    CMP	    R2,R1
    BNE	    READ_DRAM1
    
    ldr     r4,=SDRAM_BANK2_WRITE
    bl      SEGMENT_DISPLAY
    ldr	    r0,=0x55aaaa55
    ldr     r1,=DRAM2_CHECK_END-4
    ldr     r2,=DRAM2_CHECK_START-4

WRITE_DRAM2
    ADD     R2,R2,#4
    STR	    R0,[R2]
    CMP	    R2,R1
    BNE	    WRITE_DRAM2
	
    ldr     r4,=SDRAM_BANK2_READ
    bl      SEGMENT_DISPLAY
    ldr	    r3,=0x55aaaa55
    ldr     r1,=DRAM2_CHECK_END-4
    ldr     r2,=DRAM2_CHECK_START-4
READ_DRAM2
    ADD	    R2,R2,#4
    LDR	    R0,[R2]
    CMP	    R0,R3
    BNE	    DRAM_ERROR
    CMP	    R2,R1
    BNE	    READ_DRAM2
    B	    DRAM_GOOD
	;=====================================
	; LED ON DRAM CHECK FAIL
	;=====================================
DRAM_ERROR
    ORR     r4,r4,#0x0000000F
    bl      SEGMENT_DISPLAY
    B	DRAM_ERROR	
    ]
DRAM_GOOD
    ldr     r4,=SDRAM_TEST_OK
    bl      SEGMENT_DISPLAY
    ;****************************************************
    ;*	Initialize stacks				* 
    ;****************************************************
    ldr	    sp, =SVCStack	;Why?
    bl	    InitStacks

    ;****************************************************
    ;*	Setup IRQ handler				*
    ;****************************************************
    ldr	    r0,=HandleIRQ
    ldr	    r1,=IsrIRQ
    str	    r1,[r0]

    ;********************************************************
    ;*	Copy and paste RW data/zero initialized data	    *
    ;********************************************************
    LDR	    r0, =|Image$$RO$$Limit|	; Get pointer to ROM data
    LDR	    r1, =|Image$$RW$$Base|	; and RAM copy
    LDR	    r3, =|Image$$ZI$$Base|	
	;Zero init base => top of initialised data
			
    CMP	    r0, r1	    ; Check that they are different
    BEQ	    %F1
0		
    CMP	    r1, r3	    ; Copy init data
    LDRCC   r2, [r0], #4    ;--> LDRCC r2, [r0] + ADD r0, r0, #4		 
    STRCC   r2, [r1], #4    ;--> STRCC r2, [r1] + ADD r1, r1, #4
    BCC	    %B0
1		
    LDR	    r1, =|Image$$ZI$$Limit| ; Top of zero init segment
    MOV	    r2, #0
2		
    CMP	    r3, r1	    ; Zero init
    STRCC   r2, [r3], #4
    BCC	    %B2
    
    ldr     r4,=BOOT_START
    bl      SEGMENT_DISPLAY
    
    ldr     r0,=SYSCFG
    ldr     r1,=0x00            ;Disable All Cache and buffer 
    str     r1,[r0]

;    BL	    Main	       ;Don't use main() because ......
    						

;****************************************************
;*	The function for initializing stack	    *
;****************************************************
InitStacks
	;Don't use DRAM,such as stmfd,ldmfd......
	;SVCstack is initialized before
	;Under toolkit ver 2.50, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'

    mrs	    r0,cpsr
    bic	    r0,r0,#MODEMASK
    orr	    r1,r0,#UNDEFMODE|NOINT
    msr	    cpsr_cxsf,r1		;UndefMode
    ldr	    sp,=UndefStack
	
    orr	    r1,r0,#ABORTMODE|NOINT
    msr	    cpsr_cxsf,r1 	    	;AbortMode
    ldr	    sp,=AbortStack

    orr	    r1,r0,#IRQMODE|NOINT
    msr	    cpsr_cxsf,r1 	    	;IRQMode
    ldr	    sp,=IRQStack
	
    orr	    r1,r0,#FIQMODE|NOINT
    msr	    cpsr_cxsf,r1 	    	;FIQMode
    ldr	    sp,=FIQStack

    bic	    r0,r0,#MODEMASK|NOINT
    orr	    r1,r0,#SVCMODE
    msr	    cpsr_cxsf,r1 	    	;SVCMode
    ldr	    sp,=SVCStack

	;USER mode is not initialized.
    mov	    pc,lr ;The LR register may be not valid for the mode changes.
    
SEGMENT_DISPLAY
    ldr     r5,=DEBUG_BANK_ADDR
    MVN     R4,R4
    strb    R4,[R5,#0]
    mov    pc,lr    

;****************************************************
;*	The function for entering power down mode   *
;****************************************************
;void EnterPWDN(int CLKCON);
EnterPWDN
    mov	    r2,r0               ;r0=CLKCON
    ldr	    r0,=REFRESH		
    ldr	    r3,[r0]
    mov	    r1, r3
    orr	    r1, r1, #0x400000   ;self-refresh enable
    str	    r1, [r0]

    nop     ;Wait until self-refresh is issued. May not be needed.
    nop     ;If the other bus master holds the bus, ...
    nop	    ; mov r0, r0
    nop
    nop
    nop
    nop

;enter POWERDN mode
    ldr	    r0,=CLKCON
    str	    r2,[r0]

;wait until enter SL_IDLE,STOP mode and until wake-up
    mov	    r0,#0x4 
0   subs    r0,r0,#1
    bne	    %B0

;exit from DRAM/SDRAM self refresh mode.
    ldr	    r0,=REFRESH
    str	    r3,[r0]

    mov	    pc,lr

    LTORG

SMRDATA DATA
;*****************************************************************
;* Memory configuration has to be optimized for best performance *
;* The following parameter is not optimized.                     *
;*****************************************************************

;*** memory access cycle parameter strategy ***
; 1) Even FP-DRAM, EDO setting has more late fetch point by half-clock
; 2) The memory settings,here, are made the safe parameters even at 66Mhz.
; 3) FP-DRAM Parameters:tRCD=3 for tRAC, tcas=2 for pad delay, tcp=2 for bus load.
; 4) DRAM refresh rate is for 40Mhz. 
; nGCS0 Boot Flash        0x0000000
; nGCS1 SMC9113 ethernet  0x2000000
; nGCS2 USB               0x4000000
; nGCS3 FPGA              0x6000000
; nGCS4 Spare Flash       0x8000000
; nGCS5 7-Segment         0xa000000
    [ BUSWIDTH=16
	DCD 0x11111190	;Bank0=OM[1:0], Bank1~Bank7=16bit
    | ;BUSWIDTH=32
	DCD 0x222222a0	;Bank0=OM[1:0], Bank1~Bank7=32bit
    ]
	DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))	;GCS0
	DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))	;GCS1 
	DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))	;GCS2
	DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))	;GCS3
	DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))	;GCS4
	DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))	;GCS5
	[ BDRAMTYPE="DRAM" 
	    DCD ((B6_MT<<15)+(B6_Trcd<<4)+(B6_Tcas<<3)+(B6_Tcp<<2)+(B6_CAN))	;GCS6 check the MT value in parameter.a
	    DCD ((B7_MT<<15)+(B7_Trcd<<4)+(B7_Tcas<<3)+(B7_Tcp<<2)+(B7_CAN))	;GCS7
	| ;"SDRAM"
		DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))	;GCS6
		DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))	;GCS7
	]
	DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)	;REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019
	DCD 0x10			;SCLK, BANKSIZE 32M/32M
	DCD 0x20			;MRSR6 CL=2clk
	DCD 0x20			;MRSR7

	ALIGN


	AREA RamData, DATA, READWRITE

	^	(_ISR_STARTADDRESS-10240)
				
UserStack	#	2048	;0xdffd700
SVCStack	#	2048	;0xdffdf00
UndefStack	#	2048	;0xdffe700
AbortStack	#	2048	;0xdffef00
IRQStack	#	2048	;0xdfff700
FIQStack	#	0	;0xdffff00


		^	_ISR_STARTADDRESS
HandleReset	#	4   ;0xdffff00
HandleUndef	#	4   ;0xdffff04
HandleSWI	#	4   ;0xdffff08
HandlePabort	#	4   ;0xdffff0c
HandleDabort	#	4   ;0xdffff10
HandleReserved	#	4   ;0xdffff14
HandleIRQ	#	4   ;0xdffff18
HandleFIQ	#	4   ;0xdffff1c

;Don't use the label 'IntVectorTable',
;because armasm.exe cann't recognize this label correctly.
;the value is different with an address you think it may be.
;IntVectorTable
HandleADC	#	4    ;0xdffff20
HandleRTC	#	4    ;0xdffff24
HandleUTXD1	#	4    ;0xdffff28
HandleUTXD0	#	4    ;0xdffff2c
HandleSIO	#	4    ;0xdffff30
HandleIIC	#	4    ;0xdffff34
HandleURXD1	#	4    ;0xdffff38
HandleURXD0	#	4    ;0xdffff3c
HandleTIMER5	#	4    ;0xdffff40
HandleTIMER4	#	4    ;0xdffff44
HandleTIMER3	#	4    ;0xdffff48
HandleTIMER2	#	4    ;0xdffff4c
HandleTIMER1	#	4    ;0xdffff50
HandleTIMER0	#	4    ;0xdffff54
HandleUERR01	#	4    ;0xdffff58
HandleWDT	#	4    ;0xdffff5c
HandleBDMA1	#	4    ;0xdffff60
HandleBDMA0	#	4    ;0xdffff64
HandleZDMA1	#	4    ;0xdffff68
HandleZDMA0	#	4    ;0xdffff6c
HandleTICK	#	4    ;0xdffff70
HandleEINT4567	#	4    ;0xdffff74
HandleEINT3	#	4    ;0xdffff78
HandleEINT2	#	4    ;0xdffff7c
HandleEINT1	#	4    ;0xdffff80
HandleEINT0	#	4    ;0x7ffff84
HandleSWI_C     #       4   ;<----------------software interrupt C entry

		END