sysinit.s

ARM920T S3C440B 原碼

; *******************************************************
; * NAME    : SYSInit.S					*
; * Version : 05.Feb.2005				*
; * Description:					*
; *	C start up codes				*
; *	Configure memory, Initialize ISR ,stacks	*
; *	Initialize C-variables				*
; *	Fill zeros into zero-initialized C-variables	*
; *     Author: Victor Fan Created                      *
; *******************************************************
 
    GET ..\inc\option.s
    GET ..\inc\memcfg.s

;Memory Area
;GCS6 256M 16bit(32MB) DRAM/SDRAM(0xc000000-0xdffffff)
;APP    RAM=0xc000000~0xc7effff 
;44BMON RAM=0xc7f0000-0xc7fffff
;STACK	   =0xc7ffa00		   

;Interrupt Control
INTPND	    EQU	0x01e00004
INTMOD	    EQU	0x01e00008
INTMSK	    EQU	0x01e0000c
I_ISPR	    EQU	0x01e00020
I_CMST	    EQU	0x01e0001c

;Watchdog timer
WTCON	    EQU	0x01d30000

;Clock Controller
PLLCON	    EQU	0x01d80000
CLKCON	    EQU	0x01d80004
LOCKTIME    EQU	0x01d8000c
	
;Memory Controller
REFRESH	    EQU 0x01c80024

;System Configuration Register
SYSCFG      EQU 0x1c00000
NCACHBE0    EQU 0x1c00004
NCACHBE1    EQU 0x1c00008
;IO Port Controller
PCONA       EQU 0x1d20000
PCONB       EQU 0x1d20008
PCONC       EQU 0x1d20010
PCOND       EQU 0x1d2001c
PCONE       EQU 0x1d20028
PCONF       EQU 0x1d20034
PCONG       EQU 0x1d20040

;Pre-defined constants
USERMODE    EQU	0x10
FIQMODE	    EQU	0x11
IRQMODE	    EQU	0x12
SVCMODE	    EQU	0x13
ABORTMODE   EQU	0x17
UNDEFMODE   EQU	0x1b
MODEMASK    EQU	0x1f
NOINT	    EQU	0xc0

T_bit       EQU 0x20

    MACRO
$HandlerLabel HANDLER $HandleLabel

$HandlerLabel
    sub	    sp,sp,#4	    ;decrement sp(to store jump address)
    stmfd   sp!,{r0}	    ;PUSH the work register to stack(lr does't push because it return to original address)
    ldr	    r0,=$HandleLabel;load the address of HandleXXX to r0
    ldr	    r0,[r0]	    ;load the contents(service routine start address) of HandleXXX
    str	    r0,[sp,#4]	    ;store the contents(ISR) of HandleXXX to stack
    ldmfd   sp!,{r0,pc}	    ;POP the work register and pc(jump to ISR)
    MEND

    IMPORT	|Image$$RO$$Limit|  ; End of ROM code (=start of ROM data)
    IMPORT	|Image$$RW$$Base|   ; Base of RAM to initialise
    IMPORT	|Image$$ZI$$Base|   ; Base and limit of area
    IMPORT	|Image$$ZI$$Limit|  ; to zero initialise

;    IMPORT  Main    ; The main entry of mon program 					
    AREA    Init,CODE,READONLY

    ENTRY 
    b ResetHandler  ;for debug
    b HandlerUndef  ;handlerUndef
    [ SWI_DEF    
    b  SWI_Handler  ;SWI interrupt handler
    |
    b HandlerSWI    ;SWI interrupt handler
    ]
    b HandlerPabort ;handlerPAbort
    b HandlerDabort ;handlerDAbort
    b .		    ;handlerReserved
    b HandlerIRQ
    b HandlerFIQ

VECTOR_BRANCH
    ldr pc,=HandlerEINT0    ;mGA    H/W interrupt vector table
    ldr pc,=HandlerEINT1    ;	
    ldr pc,=HandlerEINT2    ;
    ldr pc,=HandlerEINT3    ;
    ldr pc,=HandlerEINT4567 ;
    ldr pc,=HandlerTICK	    ;mGA
    b .
    b .
    ldr pc,=HandlerZDMA0    ;mGB
    ldr pc,=HandlerZDMA1    ;
    ldr pc,=HandlerBDMA0    ;
    ldr pc,=HandlerBDMA1    ;
    ldr pc,=HandlerWDT	    ;
    ldr pc,=HandlerUERR01   ;mGB
    b .
    b .
    ldr pc,=HandlerTIMER0   ;mGC
    ldr pc,=HandlerTIMER1   ;
    ldr pc,=HandlerTIMER2   ;
    ldr pc,=HandlerTIMER3   ;
    ldr pc,=HandlerTIMER4   ;
    ldr pc,=HandlerTIMER5   ;mGC
    b .
    b .
    ldr pc,=HandlerURXD0    ;mGD
    ldr pc,=HandlerURXD1    ;
    ldr pc,=HandlerIIC	    ;
    ldr pc,=HandlerSIO	    ;
    ldr pc,=HandlerUTXD0    ;
    ldr pc,=HandlerUTXD1    ;mGD
    b .
    b .
    ldr pc,=HandlerRTC	    ;mGKA
    b .			    ;
    b .			    ;
    b .			    ;
    b .			    ;
    b .			    ;mGKA
    b .
    b .
    ldr pc,=HandlerADC	    ;mGKB
    b .			    ;
    b .			    ;
    b .			    ;
    b .			    ;
    b .			    ;mGKB
    b .
    b .
;0xe0=EnterPWDN
    ldr pc,=EnterPWDN

    LTORG	

HandlerFIQ	HANDLER HandleFIQ
HandlerIRQ	HANDLER HandleIRQ
HandlerUndef	HANDLER HandleUndef
HandlerSWI	HANDLER HandleSWI
HandlerDabort	HANDLER HandleDabort
HandlerPabort	HANDLER HandlePabort

HandlerADC	HANDLER HandleADC
HandlerRTC	HANDLER HandleRTC
HandlerUTXD1	HANDLER HandleUTXD1
HandlerUTXD0	HANDLER HandleUTXD0
HandlerSIO	HANDLER HandleSIO
HandlerIIC	HANDLER HandleIIC
HandlerURXD1	HANDLER HandleURXD1
HandlerURXD0	HANDLER HandleURXD0
HandlerTIMER5	HANDLER HandleTIMER5
HandlerTIMER4	HANDLER HandleTIMER4
HandlerTIMER3	HANDLER HandleTIMER3
HandlerTIMER2	HANDLER HandleTIMER2
HandlerTIMER1	HANDLER HandleTIMER1
HandlerTIMER0	HANDLER HandleTIMER0
HandlerUERR01	HANDLER HandleUERR01
HandlerWDT	HANDLER HandleWDT
HandlerBDMA1	HANDLER HandleBDMA1
HandlerBDMA0	HANDLER HandleBDMA0
HandlerZDMA1	HANDLER HandleZDMA1
HandlerZDMA0	HANDLER HandleZDMA0
HandlerTICK	HANDLER HandleTICK
HandlerEINT4567	HANDLER HandleEINT4567
HandlerEINT3	HANDLER HandleEINT3
HandlerEINT2	HANDLER HandleEINT2
HandlerEINT1	HANDLER HandleEINT1
HandlerEINT0	HANDLER HandleEINT0


;One of the following two routines can be used for non-vectored interrupt.

IsrIRQ	;using I_ISPR register.
    sub	    sp,sp,#4       ;reserved for PC
    stmfd   sp!,{r8-r9}   

	;IMPORTANT CAUTION
	;if I_ISPC isn't used properly, I_ISPR can be 0 in this routine.

    ldr	    r9,=I_ISPR
    ldr	    r9,[r9]
    mov	    r8,#0x0
0
    movs    r9,r9,lsr #1
    bcs	    %F1
    add	    r8,r8,#4
    b	    %B0

1
    ldr	    r9,=HandleADC
    add	    r9,r9,r8
    ldr	    r9,[r9]
    str	    r9,[sp,#8]
    ldmfd   sp!,{r8-r9,pc}
    [ SWI_DEF
    IMPORT  C_SWI_Handler
; Software Interrupt Handler Routine
SWI_Handler

    STMFD   sp!, {r0-r3, r12, lr}  ; Store registers
    MOV     r1, sp                 ; Set pointer to parameters
    MRS     r0, spsr               ; Get spsr
    STMFD   sp!, {r0}              ; Store spsr onto stack
    TST     r0, #T_bit             ; Occurred in Thumb state?
    LDRNEH  r0, [lr,#-2]           ; Yes: Load halfword and...
    BICNE   r0, r0, #0xFF00        ; ...extract comment field
    LDREQ   r0, [lr,#-4]           ; No: Load word and...
    BICEQ   r0, r0, #0xFF000000    ; ...extract comment field

        ; r0 now contains SWI number
        ; r1 now contains pointer to stacked registers

    BL      C_SWI_Handler          ; Call main part of handler
;    ldr     pc,=HandleSWI_C
    LDMFD   sp!, {r0}              ; Get spsr from stack
    MSR     spsr_cf, r0            ; Restore spsr
    LDMFD   sp!, {r0-r3, r12, pc}^ ; Restore registers and return
    ]
;****************************************************
;*	START					    *
;****************************************************
ResetHandler
    ldr	    r0,=WTCON	    ;watch dog disable 
    ldr	    r1,=0x0 		
    str	    r1,[r0]

    ldr	    r0,=INTMSK
    ldr	    r1,=0x07ffffff  ;all interrupt disable
    str	    r1,[r0]

    ;****************************************************
    ;*	Set clock control registers			*
    ;****************************************************
    ldr	r0,=LOCKTIME
    ldr	r1,=800	    ; count = t_lock * Fin (t_lock=200us, Fin=4MHz) = 800
    str	r1,[r0]

    [ PLLONSTART
	ldr	r0,=PLLCON			;temporary setting of PLL
	ldr	r1,=((M_DIV<<12)+(P_DIV<<4)+S_DIV)	;REF option.s
	str	r1,[r0]
    ]

    ldr	    r0,=CLKCON		
     
    ldr	    r1,=0x7ff8	    ;All unit block CLK enable	
    str	    r1,[r0]

    ;****************************************************
    ;*	Initial GPIO Register    			* 	
    ;****************************************************
    ldr     r0,=SYSCFG
    ldr     r1,=0x06            ;Enable All Cache and buffer 
    str     r1,[r0]
    
    ldr     r0,=NCACHBE0        ;All Non-Cache except Flash and SDRAM
    ldr     r1,=NCACHBE0_INIT
    str     r1,[r0]
    
    ;****************************************************
    ;*	Set memory control registers			* 	
    ;****************************************************
    
    ldr	    r0,=SMRDATA
    ldmia   r0,{r1-r13}
    ldr	    r0,=0x01c80000  ;BWSCON Address
    stmia   r0,{r1-r13}
    ;****************************************************
    ;*	Memory Test              			* 	
    ;****************************************************
    ldr     r4,=SDRAM_START_TEST
    bl      SEGMENT_DISPLAY