option.s

ARM920T S3C440B 原碼

;**********OPTIONS*******************************

_ISR_STARTADDRESS  EQU   0xdffff00    ;GCS6:256Mb DRAM/SDRAM
DRAM1_CHECK_START  EQU   0xc100000
DRAM1_CHECK_END    EQU   0xe000000
DRAM2_CHECK_START  EQU   0xe000000
DRAM2_CHECK_END    EQU   0x10000000

_RAM_STARTADDRESS EQU   0xc000000    ;from 0xc000000 - 0xe000000
;_ISR_STARTADDRESS EQU   0xc1fff00   ;GCS6:16MbDRAM
SEGMENT_BASE_ADDR  EQU   0xa000000
;DRAM2_CHECK_END    EQU   0xE000004

NCACHBE0_INIT      EQU   0xc0002000
NCACHBE1_INIT      EQU   0xc000a000

DEBUG_BANK_ADDR    EQU   0xa000000
SDRAM_START_TEST   EQU   0x00000000
SDRAM_BANK1_WRITE  EQU   0x00000011
SDRAM_BANK1_READ   EQU   0x00000012
SDRAM_BANK1_OK     EQU   0x00000010
SDRAM_BANK1_FAIL   EQU   0x0000001f
SDRAM_BANK2_WRITE  EQU   0x00000021
SDRAM_BANK2_READ   EQU   0x00000022
SDRAM_BANK2_OK     EQU   0x00000020
SDRAM_BANK2_FAIL   EQU   0x0000002f
SDRAM_TEST_OK      EQU   0x00000055
BOOT_START         EQU   0x00000000
;DEBUG_LED_0        EQU   0xff
;DEBUG_LED_1        EQU   0xff
;BUSWIDTH; 16,32
		GBLA    BUSWIDTH
BUSWIDTH	SETA    16


;"DRAM","SDRAM"
		GBLS    BDRAMTYPE
BDRAMTYPE	SETS    "SDRAM"


;This value has to be TRUE on ROM program.
;This value has to be FALSE in RAM program.
                GBLL    PLLONSTART
PLLONSTART      SETL    {TRUE}
	GBLA	PLLCLK
PLLCLK		SETA	60000000

;system clock calculation
;Fout = (8+ M_DIV)*Fin/[(2+P_DIV)*2 ^ S_DIV]
	[	PLLCLK = 40000000	
M_DIV	EQU	72	
P_DIV	EQU	3
S_DIV	EQU	2
	]
	[	PLLCLK = 60000000	
M_DIV	EQU	88	
P_DIV	EQU	6
S_DIV	EQU	1
	]

;************************************************

	END