dlxpipeline.v

这是我个人写的DLX处理器流水线的Verilog代码

//*************************************************************//
//
//                  dlxpipeline module 
//                 
//
//*************************************************************//


//`include "instfetch.v"
//`include "instdecode.v"
//`include "instexec.v"
//`include "memaccess.v"
//`include "writeback.v"

`timescale 1ns/100ps

 module dlxpipeline(clock,reset,pc,inst_in,memdata_in,memdata_out,mem_addr,mem_wr_en);
 
 input [31:0] inst_in;
 input [31:0] memdata_in;

 input clock;
 input reset;
 
 output [31:0] pc;
 output [31:0] mem_addr;
 output [31:0] memdata_out;
 output mem_wr_en;
 
 wire branch_en,reg_write_en,mem_wr_en;
 wire [4:0]   reg_add;
 wire [31:0]  pcout,ir12,npc12,ir23,npc23,ir34,ir45,mem_addr,memdata_out,loadmemdata;
 wire [31:0]  alu_branch,reg_data,a23,b23,b34,im23,alu_out34,alu_out45;
 
  assign pc = npc12;  // PC output    
  
  assign memdata_out = b34;
 
	instfetch instfetch(.clock1(clock),.alu_branch_in(alu_branch),.reset1(reset),
	
	                    .branch_en(branch_en),.inst_in1(inst_in),.irout1(ir12),.npcout1(npc12));
	
	
	
	instdecode instdecode(.npc_in2(npc12),.inst_in2(ir12),.clock2(clock),.reg_add_in(reg_add),.reg_data_in(reg_data),.reset2(reset),
                  
                        .reg_write_en(reg_write_en),.irout2(ir23),.aout2(a23),.bout2(b23),.imout2(im23),.npcout2(npc23));
                        
	                      
	instexec instexec(.ain3(a23),.bin3(b23),.imin3(im23),.inst_in3(ir23),.npcout3(npc23),.clock3(clock),.reset3(reset),.alu_out3(alu_out34),
	
	                  .bout3(b34),.inst_out3(ir34),.alu_branch_out(alu_branch),.branch_en(branch_en),.mem_wr_en(mem_wr_en));
	                  
	                  
	memaccess memaccess(.inst_in4(ir34),.readmemdata(memdata_in),.alu_in4(alu_out34),.bin4(b34),.clock4(clock),.reset4(reset),
	
	                    .inst_out4(ir45),.alu_out4(alu_out45),.loadmemdata_out(loadmemdata),.memaddress(mem_addr));  
	                    
	                    
	writeback  writeback(.alu_in5(alu_out45),.inst_in5(ir45),.clock5(clock),.reset5(reset),.loadmemdata_in(loadmemdata),
	
                       .reg_add_out(reg_add),.reg_data_out(reg_data),.reg_write_en(reg_write_en));                                    
                     
  endmodule