instdecode.v

这是我个人写的DLX处理器流水线的Verilog代码

          	if(imm16[15])                                       //  imm16<0           
          		begin
          			imout2 <= {17'b00000_0000_0000_0000,imm16_15};  //  subtration change to addition
          			if(~regs[rs1][31])                              //  regs[rs1]>0
          				aout2 <= regs[rs1];                           //  regs[rs1]->A          					
          			else                                            //  regs[rs1]<0
          				aout2 <= {1'b1,~regs[rs1][30:0]+1};           //  complemental code            				            				
          		end
          	else                                                //  imm16>0
          		begin           		                                  
                imout2 <= {1'b1,(~{16'b0000_0000_0000_0000,imm16_15}+1)};   //  complemental code,and extend to 32 bits	 
                if(~regs[rs1][31])                              //  regs[rs1]>0
          				aout2 <= regs[rs1];                           //  regs[rs1]->A          					
          			else                                            //  regs[rs1]<0
          				aout2 <= {1'b1,~regs[rs1][30:0]+1};           //  complemental code   
              end    				               	     				
     			end       			
//------------------------------------SB,SH,SW--------------------------------------------------------------	     			
	     	else if((opcode==SB)|(opcode==SH)|(opcode==SW))         
	     		begin
	     			bout2 <= regs[rd_rs2];                             //  regs[rs2_rd]->B
		     		if(~imm16[15])                                     //  imm16>0
          		begin
          			imout2 <= {16'b0000_0000_0000_0000,imm16};     //  16 bit immediate extend to 32 bits
          			if(~regs[rs1][31])                             //  regs[rs1]>0
          				aout2 <= regs[rs1];                          //  regs[rs1]->A          			
          			else                                           //  regs[rs1]<0
          				aout2 <= {1'b1,~regs[rs1][30:0]+1};          //  complemental code            				            				
          		end
          	else  
          		begin          		                                  //  imm16<0
	              imout2 <= {1'b1,(~{16'b0000_0000_0000_0000,imm16_15}+1)};   //  complemental code,and extend to 32 bits	
	              if(~regs[rs1][31])
	          				aout2 <= regs[rs1];                           //  imm16>0,regs[rs1]>0,regs[rs1]->A          			
	        			else                                              //  regs[rs1]<0
	        				aout2 <= ~regs[rs1]+1;                          //  complemental code    
	        		end  		   				               	     				
	     	  end   
//------------------------------------ADDUI,ANDI,ORI,XORI------------------------------------------------------	   	     			   			
     	  else if((opcode==ANDI)|(opcode==ORI)|(opcode==XORI)|(opcode==ADDUI))              		  
  				begin
  					aout2 <= regs[rs1];                          //  they are unsigned,regs[rs1]->A
  					imout2 <= {16'b0000_0000_0000_0000,imm16};    //  16 bit immediate extend to 32 bits
  				end
//-----------------------------------------------SUBUI---------------------------------------------------------	   	     			   			
     	  else if(opcode==SUBUI)              		  
  				begin
  					aout2 <= regs[rs1];                                 //  they are unsigned,regs[rs1]->A
  					imout2 <= {1'b1,(~{15'b000_0000_0000_0000,imm16}+1)};  //  subtration change to addition also use complemental code 
  				end  				
//-------------------------------------------LHI---------------------------------------------------------------
	      else if(opcode==LHI)              		  
  				begin
  					aout2 <= 0;                                  //  0->A
  					imout2 <= {imm16,16'b0000_0000_0000_0000};    //  put the 16 bit immediate into the high half-word
  				end         	     				
//------------------------------------------SLLI,SRLI,SRAI-----------------------------------------------------	   	     			   			
	     	else if((opcode==SLLI)|(opcode==SRLI)|(opcode==SRAI))              		  
  				begin
  					aout2 <= regs[rs1];                                             //  they are unsigned,regs[rs1]->A
  					imout2 <= {27'b000_0000_0000_0000_0000_0000_0000,imm16_5};    //  only need the low 5 bit of the immediate 
  				end		  
//----------------------------------------------BEQZ,BNEZ------------------------------------------------------	   	     			   			
	     	else if((opcode==BEQZ)|(opcode==BNEZ))         
	     		begin
	     			aout2 <= regs[rs1];                                  //  regs[rs1]->A	     			
		     		if(~imm16[15])     	          		                   //  imm16>0        
        			imout2 <= {16'b0000_0000_0000_0000,imm16};          //  only extend to 32 bits	          		          				
	          else            		                                 //  imm16<0
	            imout2 <= {1'b1,(~{16'b0000_0000_0000_0000,imm16_15}+1)};  //  complemental code,and extend to 32 bits	     				               	     				
	     	  end  
//-------------------------------------------------JALR--------------------------------------------------------	   	     			   			
	     	else if(opcode==JALR)  
	     		begin       	     		                                    
	     		  regs[31] <= npc_in2 + 3'b100;                        //  NPC + 4 -> regs[31] (PC + 8)	
	     			aout2 <= regs[rs1];                                    //  regs[rs1]-> A  
	     			imout2 <= 0;                         	     			     				               	     				
	     	  end  
//--------------------------------------------------JR---------------------------------------------------------	   	     			   			
	     	else if(opcode==JR)  
	     		begin   
	     			aout2 <= regs[rs1];                                  //  regs[rs1]->A
	     			imout2 <= 0;   	     		                                  	     			     			     				               	     				
	     	  end	     	  
//--------------------------------------------------J----------------------------------------------------------	   	     			   			
	     	else if(opcode==J)  
	     		begin	     	
	     			if(~offset[25])      
	     			  imout2 <= {6'b00_0000,offset[25:0]};                //  offset -> imout2
	     			else
	     				imout2 <= {1'b1,(~{6'b00_0000,offset[24:0]}+1)};    //  complemental code,and extend to 32 bits
	     	  end	 
//-------------------------------------------------JAL---------------------------------------------------------	   	     			   			
	     	else if(opcode==JAL)  
	     		begin
	     			regs[31] <= npc_in2 + 3'b100;                         //  NPC + 4 -> regs[31] (PC + 8)		     			
	     			if(~offset[25])      
	     			  imout2 <= {6'b00_0000,offset};                      //  offset -> imout2
	     			else
	     				imout2 <= {1'b1,(~{6'b00_0000,offset[24:0]}+1)};    //  complemental code,and extend to 32 bits
	     	  end	     	      	
//-------------------------------------------------TRAP--------------------------------------------------------	   	     			   				     	    
	     	else if(opcode==TRAP)  
	     	  begin
	     	  	npcout2 <= 3;                                         // #3 ->PC   ?????
	     	  	imout2 <= 0;
	     	  end	
//-------------------------------------------------RFE---------------------------------------------------------	   	     			   				     	  
	     	else if(opcode==RFE)  
	     	  begin
            npcout2 <= 3;                                         // #3 ->PC   ?????
            imout2 <= 0;
	     	  end	
/*-------------------------------------------------NOP---------------------------------------------------------	   	     			   				     	  
	     	else if(opcode==NOP)  	     	  	     	  	     	  	     			     		
	     		begin
            regs[0]<= 0;                                         // ??????
	     	  end	*/	     		     		
//-------------------------------------------R type instruction-------------------------------------------------
	     	else if(opcode==R_TYPE)                                                 
	     		  begin
//-------------------------------------------------ADD----------------------------------------------------------	   	     			   				     	  	     		  	
	     		  	if(func==ADD)
	     		  		begin
	     		  			if(~regs[rs1][31])     
			          		begin
			          			if(~regs[rd_rs2][31])
			          				begin
			          					aout2 <= regs[rs1];                           //  regs[rs1]>0,regs[rd_rs2]>0
			          					bout2 <= regs[rd_rs2];                       
			          				end
			          			else                                              //  regs[rd_rs2]<0
			          				bout2 <= {1'b1,~regs[rd_rs2][30:0]}+1;           //  complemental code            				            				
			          		end
			          	else            		                                  
			              aout2 <= {1'b1,~regs[rs1][30:0]+1};                  //  complemental code  
	     		  		end
//---------------------------------------------ADDU,AND,OR,XOR-------------------------------------------------	 
              else if((func==ADDU)|(func==AND_)|(func==OR_)|(func==XOR_))
	     		  		begin
	     		  			aout2 <= regs[rs1];                        //  regs[rs1] -> A
 		  		  	    bout2 <= regs[rd_rs2];                     //  regs[rd_rs2] -> B
	     		  		end
//----------------------------------------------------SUB------------------------------------------------------	 	     		  	
             else if(func==SUB)               	               
			          begin
	     		  			if(regs[rd_rs2][31])     
			          		begin
			          			if(~regs[rs1][31])
			          				begin
			          					aout2 <= regs[rs1];                           //  regs[rs1]>0,regs[rd_rs2]>0
			          					bout2 <= {1'b0,regs[rd_rs2][30:0]};            //  "-" change to "+"              
			          				end
			          			else                                              //  regs[rd_rs2]<0
			          				aout2 <= {1'b1,~regs[rs1][30:0]+1};              //  complemental code            				            				
			          		end
			          	else            		                                  
			              bout2 <= {1'b1,~regs[rd_rs2][30:0]+1};               //  complemental code  
	     		  		end 
//------------------------------------------------SUBU---------------------------------------------------------	   	     			   			
              else if(func==SUBU)               	               
			          begin	     		  						          			
			          	aout2 <= regs[rs1];                           //  regs[rs1]->A			          					            			          				       		                                  
			            bout2 <= ~regs[rd_rs2]+1;                     //  complemental code  
	     		  		end
//--------------------------------------------SLL,SRL,SRA------------------------------------------------------	   	     			   			
             else if((func==SLL)|(func==SRL)|(func==SRA))               	               
			          begin	     		  						          			
			          	aout2 <= regs[rs1];                                                  //  regs[rs1]->A			          					            			          				       		                                  
			            bout2 <= {27'b000_0000_0000_0000_0000_0000_0000,regs[rd_rs2][4:0]};  //  only need the low 5 bit of regs[rd_rs2]  
	     		  		end
//----------------------------------------SLT,SGT,SLE,SGE,SEQ,SNE-----------------------------------------------	   	     			   			
            else if((func==SLT)|(func==SGT)|(func==SLE)|(func==SGE)|(func==SEQ)|(func==SNE)) 
          	  begin	     		  						          			
		          	aout2 <= regs[rs1];                           //  regs[rs1]->A			          					            			          				       		                                  
		            bout2 <= regs[rd_rs2];                        //  regs[rd_rs2]->B 
     		  		end     		  		
            end
      end 
   end 
 endmodule