ram.v

这是我个人写的DLX处理器流水线的Verilog代码

`timescale 1ns/100ps

module RAM_BLOCK (
		adr_i,
		clk_i,
		we_i,
		data_i,
		data_o
);

	input [31:0] adr_i;
	input [31:0] data_i;
	output [31:0] data_o;
	input clk_i;
	input we_i;


	//reg [31:0] memory[2**31:0];
	
	reg [31:0] memory[65535:0];
	
	assign data_o = memory[adr_i];
	
	always @ (posedge clk_i)
	begin
		if (we_i==1'b1)
		begin
			memory[adr_i] <= data_i;     // 这里应该用非阻塞赋值
		end
	end
endmodule