instfetch.v

来自「这是我个人写的DLX处理器流水线的Verilog代码」· Verilog 代码 · 共 52 行

//*************************************************************//
//
//                   instfetch module 
//                 author: lin zheng yi 
//
//*************************************************************//

`timescale 1ns/100ps

 module instfetch(clock1,alu_branch_in,reset1,branch_en,inst_in1,irout1,npcout1);

 input clock1;
 input reset1;
 input branch_en;
 input [31:0] alu_branch_in;
 input [31:0] inst_in1;
 output [31:0] irout1;
 output [31:0] npcout1;

 reg [31:0] pc;
 reg [31:0] instmem;
 reg [31:0] instreg;
 
 wire [31:0] irout1;
 wire [31:0] npcout1;
 
 wire [31:0] inp1;
 wire [31:0] outp;                                             
 
 assign inp1 = pc + 32'b0000_0000_0000_0000_0000_0000_0000_0100;    //  a+b=s=inp1 ,b=4 (PC+4)
 
 assign outp = branch_en ? alu_branch_in : inp1;                             // mux2to1
 
 assign irout1 = instreg;  // instruction output 
 
 assign npcout1 = pc;       //  PC output

 always@(posedge clock1 or negedge reset1)
   begin
     if(~reset1)
     	 begin
     	   instreg <= 32'b0000_0000_0000_0000_0000_0000_0000_0000; 
     	   pc      <= 32'b0000_0000_0000_0000_0000_0000_0000_0000;     	       	   
     	 end     	                 
     else
     	begin
     		instreg <= inst_in1;
     		pc      <= outp;     	
     	end       
   end 
    
 endmodule