prev_cmp_davincihd.tan.qmsg

DaVinci HD CPLD Firmware Resources 这是TI原装开发板DM6467原理图的 CPLD的VHDL代码

{ "Info" "ITDB_TSU_RESULT" "davincihdcir:U1\|sync\[0\] UART2_EN CLKIN 3.851 ns register " "Info: tsu for register \"davincihdcir:U1\|sync\[0\]\" (data pin = \"UART2_EN\", clock pin = \"CLKIN\") is 3.851 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.976 ns + Longest pin register " "Info: + Longest pin to register delay is 6.976 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns UART2_EN 1 PIN PIN_3 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_3; Fanout = 2; PIN Node = 'UART2_EN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART2_EN } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.783 ns) + CELL(1.061 ns) 6.976 ns davincihdcir:U1\|sync\[0\] 2 REG LC_X4_Y3_N2 3 " "Info: 2: + IC(4.783 ns) + CELL(1.061 ns) = 6.976 ns; Loc. = LC_X4_Y3_N2; Fanout = 3; REG Node = 'davincihdcir:U1\|sync\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.844 ns" { UART2_EN davincihdcir:U1|sync[0] } "NODE_NAME" } } { "davincihdcir.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihdcir.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns ( 31.44 % ) " "Info: Total cell delay = 2.193 ns ( 31.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.783 ns ( 68.56 % ) " "Info: Total interconnect delay = 4.783 ns ( 68.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.976 ns" { UART2_EN davincihdcir:U1|sync[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.976 ns" { UART2_EN {} UART2_EN~combout {} davincihdcir:U1|sync[0] {} } { 0.000ns 0.000ns 4.783ns } { 0.000ns 1.132ns 1.061ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "davincihdcir.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihdcir.vhd" 84 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN destination 3.458 ns - Shortest register " "Info: - Shortest clock path from clock \"CLKIN\" to destination register is 3.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLKIN 1 CLK PIN_62 45 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 45; CLK Node = 'CLKIN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLKIN } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 102 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(0.918 ns) 3.458 ns davincihdcir:U1\|sync\[0\] 2 REG LC_X4_Y3_N2 3 " "Info: 2: + IC(1.377 ns) + CELL(0.918 ns) = 3.458 ns; Loc. = LC_X4_Y3_N2; Fanout = 3; REG Node = 'davincihdcir:U1\|sync\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.295 ns" { CLKIN davincihdcir:U1|sync[0] } "NODE_NAME" } } { "davincihdcir.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihdcir.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 60.18 % ) " "Info: Total cell delay = 2.081 ns ( 60.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.377 ns ( 39.82 % ) " "Info: Total interconnect delay = 1.377 ns ( 39.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLKIN davincihdcir:U1|sync[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLKIN {} CLKIN~combout {} davincihdcir:U1|sync[0] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.976 ns" { UART2_EN davincihdcir:U1|sync[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.976 ns" { UART2_EN {} UART2_EN~combout {} davincihdcir:U1|sync[0] {} } { 0.000ns 0.000ns 4.783ns } { 0.000ns 1.132ns 1.061ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLKIN davincihdcir:U1|sync[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLKIN {} CLKIN~combout {} davincihdcir:U1|sync[0] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLKIN VID_INLO_S1 Reg1\[5\] 15.574 ns register " "Info: tco from clock \"CLKIN\" to destination pin \"VID_INLO_S1\" through register \"Reg1\[5\]\" is 15.574 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN source 7.483 ns + Longest register " "Info: + Longest clock path from clock \"CLKIN\" to source register is 7.483 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLKIN 1 CLK PIN_62 45 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 45; CLK Node = 'CLKIN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLKIN } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 102 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(1.294 ns) 3.834 ns sync_scl\[3\] 2 REG LC_X2_Y3_N8 59 " "Info: 2: + IC(1.377 ns) + CELL(1.294 ns) = 3.834 ns; Loc. = LC_X2_Y3_N8; Fanout = 59; REG Node = 'sync_scl\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.671 ns" { CLKIN sync_scl[3] } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 232 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.731 ns) + CELL(0.918 ns) 7.483 ns Reg1\[5\] 3 REG LC_X5_Y3_N5 5 " "Info: 3: + IC(2.731 ns) + CELL(0.918 ns) = 7.483 ns; Loc. = LC_X5_Y3_N5; Fanout = 5; REG Node = 'Reg1\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.649 ns" { sync_scl[3] Reg1[5] } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 742 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 45.10 % ) " "Info: Total cell delay = 3.375 ns ( 45.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.108 ns ( 54.90 % ) " "Info: Total interconnect delay = 4.108 ns ( 54.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.483 ns" { CLKIN sync_scl[3] Reg1[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.483 ns" { CLKIN {} CLKIN~combout {} sync_scl[3] {} Reg1[5] {} } { 0.000ns 0.000ns 1.377ns 2.731ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 742 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.715 ns + Longest register pin " "Info: + Longest register to pin delay is 7.715 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Reg1\[5\] 1 REG LC_X5_Y3_N5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y3_N5; Fanout = 5; REG Node = 'Reg1\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Reg1[5] } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 742 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.094 ns) + CELL(0.914 ns) 3.008 ns Enable_HD_Y~0 2 COMB LC_X6_Y1_N4 1 " "Info: 2: + IC(2.094 ns) + CELL(0.914 ns) = 3.008 ns; Loc. = LC_X6_Y1_N4; Fanout = 1; COMB Node = 'Enable_HD_Y~0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.008 ns" { Reg1[5] Enable_HD_Y~0 } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 163 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.385 ns) + CELL(2.322 ns) 7.715 ns VID_INLO_S1 3 PIN PIN_58 0 " "Info: 3: + IC(2.385 ns) + CELL(2.322 ns) = 7.715 ns; Loc. = PIN_58; Fanout = 0; PIN Node = 'VID_INLO_S1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.707 ns" { Enable_HD_Y~0 VID_INLO_S1 } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.236 ns ( 41.94 % ) " "Info: Total cell delay = 3.236 ns ( 41.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.479 ns ( 58.06 % ) " "Info: Total interconnect delay = 4.479 ns ( 58.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.715 ns" { Reg1[5] Enable_HD_Y~0 VID_INLO_S1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.715 ns" { Reg1[5] {} Enable_HD_Y~0 {} VID_INLO_S1 {} } { 0.000ns 2.094ns 2.385ns } { 0.000ns 0.914ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.483 ns" { CLKIN sync_scl[3] Reg1[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.483 ns" { CLKIN {} CLKIN~combout {} sync_scl[3] {} Reg1[5] {} } { 0.000ns 0.000ns 1.377ns 2.731ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.715 ns" { Reg1[5] Enable_HD_Y~0 VID_INLO_S1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.715 ns" { Reg1[5] {} Enable_HD_Y~0 {} VID_INLO_S1 {} } { 0.000ns 2.094ns 2.385ns } { 0.000ns 0.914ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "VIDEO_OUT_EN0 VIDOUT_LO_S0 11.426 ns Longest " "Info: Longest tpd from source pin \"VIDEO_OUT_EN0\" to destination pin \"VIDOUT_LO_S0\" is 11.426 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns VIDEO_OUT_EN0 1 PIN PIN_54 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_54; Fanout = 2; PIN Node = 'VIDEO_OUT_EN0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { VIDEO_OUT_EN0 } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.771 ns) + CELL(0.200 ns) 6.103 ns Enable_ADV_S~0 2 COMB LC_X5_Y3_N1 1 " "Info: 2: + IC(4.771 ns) + CELL(0.200 ns) = 6.103 ns; Loc. = LC_X5_Y3_N1; Fanout = 1; COMB Node = 'Enable_ADV_S~0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.971 ns" { VIDEO_OUT_EN0 Enable_ADV_S~0 } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 165 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.001 ns) + CELL(2.322 ns) 11.426 ns VIDOUT_LO_S0 3 PIN PIN_70 0 " "Info: 3: + IC(3.001 ns) + CELL(2.322 ns) = 11.426 ns; Loc. = PIN_70; Fanout = 0; PIN Node = 'VIDOUT_LO_S0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.323 ns" { Enable_ADV_S~0 VIDOUT_LO_S0 } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.654 ns ( 31.98 % ) " "Info: Total cell delay = 3.654 ns ( 31.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.772 ns ( 68.02 % ) " "Info: Total interconnect delay = 7.772 ns ( 68.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.426 ns" { VIDEO_OUT_EN0 Enable_ADV_S~0 VIDOUT_LO_S0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.426 ns" { VIDEO_OUT_EN0 {} VIDEO_OUT_EN0~combout {} Enable_ADV_S~0 {} VIDOUT_LO_S0 {} } { 0.000ns 0.000ns 4.771ns 3.001ns } { 0.000ns 1.132ns 0.200ns 2.322ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "sync_sda\[0\] PIN_I2C_SDA_IN CLKIN -2.011 ns register " "Info: th for register \"sync_sda\[0\]\" (data pin = \"PIN_I2C_SDA_IN\", clock pin = \"CLKIN\") is -2.011 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN destination 3.458 ns + Longest register " "Info: + Longest clock path from clock \"CLKIN\" to destination register is 3.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLKIN 1 CLK PIN_62 45 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 45; CLK Node = 'CLKIN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLKIN } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 102 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(0.918 ns) 3.458 ns sync_sda\[0\] 2 REG LC_X2_Y4_N4 1 " "Info: 2: + IC(1.377 ns) + CELL(0.918 ns) = 3.458 ns; Loc. = LC_X2_Y4_N4; Fanout = 1; REG Node = 'sync_sda\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.295 ns" { CLKIN sync_sda[0] } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 517 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 60.18 % ) " "Info: Total cell delay = 2.081 ns ( 60.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.377 ns ( 39.82 % ) " "Info: Total interconnect delay = 1.377 ns ( 39.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLKIN sync_sda[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLKIN {} CLKIN~combout {} sync_sda[0] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 517 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.690 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.690 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns PIN_I2C_SDA_IN 1 PIN PIN_99 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_99; Fanout = 1; PIN Node = 'PIN_I2C_SDA_IN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PIN_I2C_SDA_IN } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.967 ns) + CELL(0.591 ns) 5.690 ns sync_sda\[0\] 2 REG LC_X2_Y4_N4 1 " "Info: 2: + IC(3.967 ns) + CELL(0.591 ns) = 5.690 ns; Loc. = LC_X2_Y4_N4; Fanout = 1; REG Node = 'sync_sda\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.558 ns" { PIN_I2C_SDA_IN sync_sda[0] } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 517 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.723 ns ( 30.28 % ) " "Info: Total cell delay = 1.723 ns ( 30.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.967 ns ( 69.72 % ) " "Info: Total interconnect delay = 3.967 ns ( 69.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.690 ns" { PIN_I2C_SDA_IN sync_sda[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.690 ns" { PIN_I2C_SDA_IN {} PIN_I2C_SDA_IN~combout {} sync_sda[0] {} } { 0.000ns 0.000ns 3.967ns } { 0.000ns 1.132ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLKIN sync_sda[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLKIN {} CLKIN~combout {} sync_sda[0] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.690 ns" { PIN_I2C_SDA_IN sync_sda[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.690 ns" { PIN_I2C_SDA_IN {} PIN_I2C_SDA_IN~combout {} sync_sda[0] {} } { 0.000ns 0.000ns 3.967ns } { 0.000ns 1.132ns 0.591ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}