prev_cmp_davincihd.tan.qmsg

DaVinci HD CPLD Firmware Resources 这是TI原装开发板DM6467原理图的 CPLD的VHDL代码

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "sync_sda\[3\] " "Info: Detected ripple clock \"sync_sda\[3\]\" as buffer" {  } { { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 231 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sync_sda\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "sync_scl\[3\] " "Info: Detected ripple clock \"sync_scl\[3\]\" as buffer" {  } { { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 232 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sync_scl\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLKIN register Reg0\[5\] register davincihdcir:U1\|sync\[0\] 35.434 ns " "Info: Slack time is 35.434 ns for clock \"CLKIN\" between source register \"Reg0\[5\]\" and destination register \"davincihdcir:U1\|sync\[0\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "80.22 MHz 12.466 ns " "Info: Fmax is 80.22 MHz (period= 12.466 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "36.933 ns + Largest register register " "Info: + Largest register to register requirement is 36.933 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "41.667 ns + " "Info: + Setup relationship between source and destination is 41.667 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 83.333 ns " "Info: + Latch edge is 83.333 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLKIN 83.333 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"CLKIN\" is 83.333 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 41.666 ns " "Info: - Launch edge is 41.666 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLKIN 83.333 ns 41.666 ns inverted 50 " "Info: Clock period of Source clock \"CLKIN\" is 83.333 ns with inverted offset of 41.666 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.025 ns + Largest " "Info: + Largest clock skew is -4.025 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN destination 3.458 ns + Shortest register " "Info: + Shortest clock path from clock \"CLKIN\" to destination register is 3.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLKIN 1 CLK PIN_62 45 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 45; CLK Node = 'CLKIN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLKIN } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 102 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(0.918 ns) 3.458 ns davincihdcir:U1\|sync\[0\] 2 REG LC_X4_Y3_N2 3 " "Info: 2: + IC(1.377 ns) + CELL(0.918 ns) = 3.458 ns; Loc. = LC_X4_Y3_N2; Fanout = 3; REG Node = 'davincihdcir:U1\|sync\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.295 ns" { CLKIN davincihdcir:U1|sync[0] } "NODE_NAME" } } { "davincihdcir.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihdcir.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 60.18 % ) " "Info: Total cell delay = 2.081 ns ( 60.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.377 ns ( 39.82 % ) " "Info: Total interconnect delay = 1.377 ns ( 39.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLKIN davincihdcir:U1|sync[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLKIN {} CLKIN~combout {} davincihdcir:U1|sync[0] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN source 7.483 ns - Longest register " "Info: - Longest clock path from clock \"CLKIN\" to source register is 7.483 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLKIN 1 CLK PIN_62 45 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 45; CLK Node = 'CLKIN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLKIN } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 102 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(1.294 ns) 3.834 ns sync_scl\[3\] 2 REG LC_X2_Y3_N8 59 " "Info: 2: + IC(1.377 ns) + CELL(1.294 ns) = 3.834 ns; Loc. = LC_X2_Y3_N8; Fanout = 59; REG Node = 'sync_scl\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.671 ns" { CLKIN sync_scl[3] } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 232 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.731 ns) + CELL(0.918 ns) 7.483 ns Reg0\[5\] 3 REG LC_X4_Y3_N8 3 " "Info: 3: + IC(2.731 ns) + CELL(0.918 ns) = 7.483 ns; Loc. = LC_X4_Y3_N8; Fanout = 3; REG Node = 'Reg0\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.649 ns" { sync_scl[3] Reg0[5] } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 742 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 45.10 % ) " "Info: Total cell delay = 3.375 ns ( 45.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.108 ns ( 54.90 % ) " "Info: Total interconnect delay = 4.108 ns ( 54.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.483 ns" { CLKIN sync_scl[3] Reg0[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.483 ns" { CLKIN {} CLKIN~combout {} sync_scl[3] {} Reg0[5] {} } { 0.000ns 0.000ns 1.377ns 2.731ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLKIN davincihdcir:U1|sync[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLKIN {} CLKIN~combout {} davincihdcir:U1|sync[0] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.483 ns" { CLKIN sync_scl[3] Reg0[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.483 ns" { CLKIN {} CLKIN~combout {} sync_scl[3] {} Reg0[5] {} } { 0.000ns 0.000ns 1.377ns 2.731ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 742 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns - " "Info: - Micro setup delay of destination is 0.333 ns" {  } { { "davincihdcir.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihdcir.vhd" 84 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLKIN davincihdcir:U1|sync[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLKIN {} CLKIN~combout {} davincihdcir:U1|sync[0] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.483 ns" { CLKIN sync_scl[3] Reg0[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.483 ns" { CLKIN {} CLKIN~combout {} sync_scl[3] {} Reg0[5] {} } { 0.000ns 0.000ns 1.377ns 2.731ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.499 ns - Longest register register " "Info: - Longest register to register delay is 1.499 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Reg0\[5\] 1 REG LC_X4_Y3_N8 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y3_N8; Fanout = 3; REG Node = 'Reg0\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Reg0[5] } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 742 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.908 ns) + CELL(0.591 ns) 1.499 ns davincihdcir:U1\|sync\[0\] 2 REG LC_X4_Y3_N2 3 " "Info: 2: + IC(0.908 ns) + CELL(0.591 ns) = 1.499 ns; Loc. = LC_X4_Y3_N2; Fanout = 3; REG Node = 'davincihdcir:U1\|sync\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.499 ns" { Reg0[5] davincihdcir:U1|sync[0] } "NODE_NAME" } } { "davincihdcir.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihdcir.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.591 ns ( 39.43 % ) " "Info: Total cell delay = 0.591 ns ( 39.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.908 ns ( 60.57 % ) " "Info: Total interconnect delay = 0.908 ns ( 60.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.499 ns" { Reg0[5] davincihdcir:U1|sync[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.499 ns" { Reg0[5] {} davincihdcir:U1|sync[0] {} } { 0.000ns 0.908ns } { 0.000ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLKIN davincihdcir:U1|sync[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLKIN {} CLKIN~combout {} davincihdcir:U1|sync[0] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.483 ns" { CLKIN sync_scl[3] Reg0[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.483 ns" { CLKIN {} CLKIN~combout {} sync_scl[3] {} Reg0[5] {} } { 0.000ns 0.000ns 1.377ns 2.731ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.499 ns" { Reg0[5] davincihdcir:U1|sync[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.499 ns" { Reg0[5] {} davincihdcir:U1|sync[0] {} } { 0.000ns 0.908ns } { 0.000ns 0.591ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "CLKIN register tc_sync_ponrs\[1\] register tc_sync_ponrs\[2\] 1.377 ns " "Info: Minimum slack time is 1.377 ns for clock \"CLKIN\" between source register \"tc_sync_ponrs\[1\]\" and destination register \"tc_sync_ponrs\[2\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.222 ns + Shortest register register " "Info: + Shortest register to register delay is 1.222 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tc_sync_ponrs\[1\] 1 REG LC_X7_Y3_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y3_N7; Fanout = 1; REG Node = 'tc_sync_ponrs\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { tc_sync_ponrs[1] } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 302 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.942 ns) + CELL(0.280 ns) 1.222 ns tc_sync_ponrs\[2\] 2 REG LC_X7_Y3_N9 6 " "Info: 2: + IC(0.942 ns) + CELL(0.280 ns) = 1.222 ns; Loc. = LC_X7_Y3_N9; Fanout = 6; REG Node = 'tc_sync_ponrs\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.222 ns" { tc_sync_ponrs[1] tc_sync_ponrs[2] } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 302 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.280 ns ( 22.91 % ) " "Info: Total cell delay = 0.280 ns ( 22.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.942 ns ( 77.09 % ) " "Info: Total interconnect delay = 0.942 ns ( 77.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.222 ns" { tc_sync_ponrs[1] tc_sync_ponrs[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.222 ns" { tc_sync_ponrs[1] {} tc_sync_ponrs[2] {} } { 0.000ns 0.942ns } { 0.000ns 0.280ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.155 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.155 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLKIN 83.333 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"CLKIN\" is 83.333 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLKIN 83.333 ns 0.000 ns  50 " "Info: Clock period of Source clock \"CLKIN\" is 83.333 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN destination 3.458 ns + Longest register " "Info: + Longest clock path from clock \"CLKIN\" to destination register is 3.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLKIN 1 CLK PIN_62 45 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 45; CLK Node = 'CLKIN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLKIN } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 102 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(0.918 ns) 3.458 ns tc_sync_ponrs\[2\] 2 REG LC_X7_Y3_N9 6 " "Info: 2: + IC(1.377 ns) + CELL(0.918 ns) = 3.458 ns; Loc. = LC_X7_Y3_N9; Fanout = 6; REG Node = 'tc_sync_ponrs\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.295 ns" { CLKIN tc_sync_ponrs[2] } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 302 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 60.18 % ) " "Info: Total cell delay = 2.081 ns ( 60.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.377 ns ( 39.82 % ) " "Info: Total interconnect delay = 1.377 ns ( 39.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLKIN tc_sync_ponrs[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLKIN {} CLKIN~combout {} tc_sync_ponrs[2] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN source 3.458 ns - Shortest register " "Info: - Shortest clock path from clock \"CLKIN\" to source register is 3.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLKIN 1 CLK PIN_62 45 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 45; CLK Node = 'CLKIN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLKIN } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 102 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(0.918 ns) 3.458 ns tc_sync_ponrs\[1\] 2 REG LC_X7_Y3_N7 1 " "Info: 2: + IC(1.377 ns) + CELL(0.918 ns) = 3.458 ns; Loc. = LC_X7_Y3_N7; Fanout = 1; REG Node = 'tc_sync_ponrs\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.295 ns" { CLKIN tc_sync_ponrs[1] } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 302 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 60.18 % ) " "Info: Total cell delay = 2.081 ns ( 60.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.377 ns ( 39.82 % ) " "Info: Total interconnect delay = 1.377 ns ( 39.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLKIN tc_sync_ponrs[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLKIN {} CLKIN~combout {} tc_sync_ponrs[1] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLKIN tc_sync_ponrs[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLKIN {} CLKIN~combout {} tc_sync_ponrs[2] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLKIN tc_sync_ponrs[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLKIN {} CLKIN~combout {} tc_sync_ponrs[1] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 302 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 302 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLKIN tc_sync_ponrs[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLKIN {} CLKIN~combout {} tc_sync_ponrs[2] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLKIN tc_sync_ponrs[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLKIN {} CLKIN~combout {} tc_sync_ponrs[1] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.222 ns" { tc_sync_ponrs[1] tc_sync_ponrs[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.222 ns" { tc_sync_ponrs[1] {} tc_sync_ponrs[2] {} } { 0.000ns 0.942ns } { 0.000ns 0.280ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLKIN tc_sync_ponrs[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLKIN {} CLKIN~combout {} tc_sync_ponrs[2] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLKIN tc_sync_ponrs[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLKIN {} CLKIN~combout {} tc_sync_ponrs[1] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}