prev_cmp_davincihd.qmsg

DaVinci HD CPLD Firmware Resources 这是TI原装开发板DM6467原理图的 CPLD的VHDL代码

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.969 ns register register " "Info: Estimated most critical path is register to register delay of 5.969 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ADDR_IN_BUF\[7\] 1 REG LAB_X6_Y2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X6_Y2; Fanout = 2; REG Node = 'ADDR_IN_BUF\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ADDR_IN_BUF[7] } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 625 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.232 ns) + CELL(0.200 ns) 1.432 ns Equal3~63 2 COMB LAB_X6_Y2 3 " "Info: 2: + IC(1.232 ns) + CELL(0.200 ns) = 1.432 ns; Loc. = LAB_X6_Y2; Fanout = 3; COMB Node = 'Equal3~63'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.432 ns" { ADDR_IN_BUF[7] Equal3~63 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.056 ns) + CELL(0.200 ns) 2.688 ns WRONG_ADDR~92 3 COMB LAB_X6_Y2 4 " "Info: 3: + IC(1.056 ns) + CELL(0.200 ns) = 2.688 ns; Loc. = LAB_X6_Y2; Fanout = 4; COMB Node = 'WRONG_ADDR~92'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.256 ns" { Equal3~63 WRONG_ADDR~92 } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 180 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.056 ns) + CELL(0.200 ns) 3.944 ns READ_OR_WRITE~378 4 COMB LAB_X6_Y2 3 " "Info: 4: + IC(1.056 ns) + CELL(0.200 ns) = 3.944 ns; Loc. = LAB_X6_Y2; Fanout = 3; COMB Node = 'READ_OR_WRITE~378'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.256 ns" { WRONG_ADDR~92 READ_OR_WRITE~378 } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 184 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(1.243 ns) 5.969 ns REG_ADDR\[0\] 5 REG LAB_X6_Y2 11 " "Info: 5: + IC(0.782 ns) + CELL(1.243 ns) = 5.969 ns; Loc. = LAB_X6_Y2; Fanout = 11; REG Node = 'REG_ADDR\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.025 ns" { READ_OR_WRITE~378 REG_ADDR[0] } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 638 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.843 ns ( 30.88 % ) " "Info: Total cell delay = 1.843 ns ( 30.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.126 ns ( 69.12 % ) " "Info: Total interconnect delay = 4.126 ns ( 69.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.969 ns" { ADDR_IN_BUF[7] Equal3~63 WRONG_ADDR~92 READ_OR_WRITE~378 REG_ADDR[0] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "15 " "Info: Average interconnect usage is 15% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "15 X0_Y0 X8_Y5 " "Info: Peak interconnect usage is 15% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sync_scl\[3\] " "Info: Node sync_scl\[3\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear START " "Info: Port clear -- assigned as a global for destination node START -- routed using non-global resources" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { START } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 177 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { START } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sync_scl[3] } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 232 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sync_scl[3] } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0 "" 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "Reg0\[1\] (inverted) " "Info: Following pins have the same output enable: Reg0\[1\] (inverted)" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional HDD_PWR_EN 3.3-V LVTTL " "Info: Type bidirectional pin HDD_PWR_EN uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { HDD_PWR_EN } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "HDD_PWR_EN" } } } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 83 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { HDD_PWR_EN } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { HDD_PWR_EN } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "USB_VBUS (inverted) " "Info: Following pins have the same output enable: USB_VBUS (inverted)" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRV_VBUS 3.3-V LVTTL " "Info: Type bidirectional pin DRV_VBUS uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { DRV_VBUS } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "DRV_VBUS" } } } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 92 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRV_VBUS } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DRV_VBUS } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "tc_scl_low (inverted) " "Info: Following pins have the same output enable: tc_scl_low (inverted)" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional PIN_I2C_SCL 3.3-V LVTTL " "Info: Type bidirectional pin PIN_I2C_SCL uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72/quartus/bin/pin_planner.ppl" { PIN_I2C_SCL } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "PIN_I2C_SCL" } } } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 103 -1 0 } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PIN_I2C_SCL } "NODE_NAME" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PIN_I2C_SCL } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/fpga/davincihd_reve_ver5/davincihd.fit.smsg " "Info: Generated suppressed messages file C:/fpga/davincihd_reve_ver5/davincihd.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "167 " "Info: Allocated 167 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 08 18:02:22 2008 " "Info: Processing ended: Tue Apr 08 18:02:22 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}