prev_cmp_davincihd.qmsg

DaVinci HD CPLD Firmware Resources 这是TI原装开发板DM6467原理图的 CPLD的VHDL代码

{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLKIN Global clock in PIN 62 " "Info: Automatically promoted signal \"CLKIN\" to use Global clock in PIN 62" {  } { { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 102 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sync_scl\[3\] Global clock " "Info: Automatically promoted some destinations of signal \"sync_scl\[3\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sync_scl\[3\] " "Info: Destination \"sync_scl\[3\]\" may be non-global or may not use global clock" {  } { { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 232 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 232 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sync_sda\[3\] Global clock " "Info: Automatically promoted some destinations of signal \"sync_sda\[3\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sync_sda\[3\] " "Info: Destination \"sync_sda\[3\]\" may be non-global or may not use global clock" {  } { { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 231 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "DATA_IN_BUF\[0\] " "Info: Destination \"DATA_IN_BUF\[0\]\" may be non-global or may not use global clock" {  } { { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 684 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ADDR_IN_BUF\[0\] " "Info: Destination \"ADDR_IN_BUF\[0\]\" may be non-global or may not use global clock" {  } { { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 625 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 231 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "Reset_SYSTEM~0 Global clock " "Info: Automatically promoted some destinations of signal \"Reset_SYSTEM~0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "SYS_RESETn " "Info: Destination \"SYS_RESETn\" may be non-global or may not use global clock" {  } { { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 78 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "I2C_SDA_OUT~53 " "Info: Destination \"I2C_SDA_OUT~53\" may be non-global or may not use global clock" {  } { { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 105 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 146 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Extra Info: Moving registers into LUTs to improve timing and density" {  } {  } 1 0 "Moving registers into LUTs to improve timing and density" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}