davincihd.tan.qmsg

DaVinci HD CPLD Firmware Resources 这是TI原装开发板DM6467原理图的 CPLD的VHDL代码

{ "Info" "ITDB_TSU_RESULT" "davincihdcir:U1\|sync\[0\] IR_IN CLKIN 3.897 ns register " "Info: tsu for register \"davincihdcir:U1\|sync\[0\]\" (data pin = \"IR_IN\", clock pin = \"CLKIN\") is 3.897 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.022 ns + Longest pin register " "Info: + Longest pin to register delay is 7.022 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns IR_IN 1 PIN PIN_51 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_51; Fanout = 2; PIN Node = 'IR_IN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { IR_IN } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.829 ns) + CELL(1.061 ns) 7.022 ns davincihdcir:U1\|sync\[0\] 2 REG LC_X4_Y2_N9 3 " "Info: 2: + IC(4.829 ns) + CELL(1.061 ns) = 7.022 ns; Loc. = LC_X4_Y2_N9; Fanout = 3; REG Node = 'davincihdcir:U1\|sync\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.890 ns" { IR_IN davincihdcir:U1|sync[0] } "NODE_NAME" } } { "davincihdcir.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihdcir.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns ( 31.23 % ) " "Info: Total cell delay = 2.193 ns ( 31.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.829 ns ( 68.77 % ) " "Info: Total interconnect delay = 4.829 ns ( 68.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.022 ns" { IR_IN davincihdcir:U1|sync[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.022 ns" { IR_IN {} IR_IN~combout {} davincihdcir:U1|sync[0] {} } { 0.000ns 0.000ns 4.829ns } { 0.000ns 1.132ns 1.061ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "davincihdcir.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihdcir.vhd" 84 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN destination 3.458 ns - Shortest register " "Info: - Shortest clock path from clock \"CLKIN\" to destination register is 3.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLKIN 1 CLK PIN_62 45 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 45; CLK Node = 'CLKIN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLKIN } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 102 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(0.918 ns) 3.458 ns davincihdcir:U1\|sync\[0\] 2 REG LC_X4_Y2_N9 3 " "Info: 2: + IC(1.377 ns) + CELL(0.918 ns) = 3.458 ns; Loc. = LC_X4_Y2_N9; Fanout = 3; REG Node = 'davincihdcir:U1\|sync\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.295 ns" { CLKIN davincihdcir:U1|sync[0] } "NODE_NAME" } } { "davincihdcir.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihdcir.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 60.18 % ) " "Info: Total cell delay = 2.081 ns ( 60.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.377 ns ( 39.82 % ) " "Info: Total interconnect delay = 1.377 ns ( 39.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLKIN davincihdcir:U1|sync[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLKIN {} CLKIN~combout {} davincihdcir:U1|sync[0] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.022 ns" { IR_IN davincihdcir:U1|sync[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.022 ns" { IR_IN {} IR_IN~combout {} davincihdcir:U1|sync[0] {} } { 0.000ns 0.000ns 4.829ns } { 0.000ns 1.132ns 1.061ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLKIN davincihdcir:U1|sync[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLKIN {} CLKIN~combout {} davincihdcir:U1|sync[0] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLKIN VID_INHI_S1 Reg1\[5\] 15.667 ns register " "Info: tco from clock \"CLKIN\" to destination pin \"VID_INHI_S1\" through register \"Reg1\[5\]\" is 15.667 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN source 7.483 ns + Longest register " "Info: + Longest clock path from clock \"CLKIN\" to source register is 7.483 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLKIN 1 CLK PIN_62 45 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 45; CLK Node = 'CLKIN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLKIN } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 102 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(1.294 ns) 3.834 ns sync_scl\[3\] 2 REG LC_X2_Y3_N7 59 " "Info: 2: + IC(1.377 ns) + CELL(1.294 ns) = 3.834 ns; Loc. = LC_X2_Y3_N7; Fanout = 59; REG Node = 'sync_scl\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.671 ns" { CLKIN sync_scl[3] } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 232 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.731 ns) + CELL(0.918 ns) 7.483 ns Reg1\[5\] 3 REG LC_X5_Y2_N6 5 " "Info: 3: + IC(2.731 ns) + CELL(0.918 ns) = 7.483 ns; Loc. = LC_X5_Y2_N6; Fanout = 5; REG Node = 'Reg1\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.649 ns" { sync_scl[3] Reg1[5] } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 742 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 45.10 % ) " "Info: Total cell delay = 3.375 ns ( 45.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.108 ns ( 54.90 % ) " "Info: Total interconnect delay = 4.108 ns ( 54.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.483 ns" { CLKIN sync_scl[3] Reg1[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.483 ns" { CLKIN {} CLKIN~combout {} sync_scl[3] {} Reg1[5] {} } { 0.000ns 0.000ns 1.377ns 2.731ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 742 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.808 ns + Longest register pin " "Info: + Longest register to pin delay is 7.808 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Reg1\[5\] 1 REG LC_X5_Y2_N6 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N6; Fanout = 5; REG Node = 'Reg1\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Reg1[5] } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 742 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.656 ns) + CELL(0.511 ns) 3.167 ns Enable_HD_C~0 2 COMB LC_X2_Y3_N8 1 " "Info: 2: + IC(2.656 ns) + CELL(0.511 ns) = 3.167 ns; Loc. = LC_X2_Y3_N8; Fanout = 1; COMB Node = 'Enable_HD_C~0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.167 ns" { Reg1[5] Enable_HD_C~0 } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.319 ns) + CELL(2.322 ns) 7.808 ns VID_INHI_S1 3 PIN PIN_67 0 " "Info: 3: + IC(2.319 ns) + CELL(2.322 ns) = 7.808 ns; Loc. = PIN_67; Fanout = 0; PIN Node = 'VID_INHI_S1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.641 ns" { Enable_HD_C~0 VID_INHI_S1 } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.833 ns ( 36.28 % ) " "Info: Total cell delay = 2.833 ns ( 36.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.975 ns ( 63.72 % ) " "Info: Total interconnect delay = 4.975 ns ( 63.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.808 ns" { Reg1[5] Enable_HD_C~0 VID_INHI_S1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.808 ns" { Reg1[5] {} Enable_HD_C~0 {} VID_INHI_S1 {} } { 0.000ns 2.656ns 2.319ns } { 0.000ns 0.511ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.483 ns" { CLKIN sync_scl[3] Reg1[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.483 ns" { CLKIN {} CLKIN~combout {} sync_scl[3] {} Reg1[5] {} } { 0.000ns 0.000ns 1.377ns 2.731ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.808 ns" { Reg1[5] Enable_HD_C~0 VID_INHI_S1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.808 ns" { Reg1[5] {} Enable_HD_C~0 {} VID_INHI_S1 {} } { 0.000ns 2.656ns 2.319ns } { 0.000ns 0.511ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "EXT_EMIF_MODE DC_P3_DETECTn 11.987 ns Longest " "Info: Longest tpd from source pin \"EXT_EMIF_MODE\" to destination pin \"DC_P3_DETECTn\" is 11.987 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns EXT_EMIF_MODE 1 PIN PIN_86 4 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_86; Fanout = 4; PIN Node = 'EXT_EMIF_MODE'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { EXT_EMIF_MODE } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.286 ns) + CELL(0.914 ns) 6.332 ns Enable_ATA~37 2 COMB LC_X4_Y4_N5 3 " "Info: 2: + IC(4.286 ns) + CELL(0.914 ns) = 6.332 ns; Loc. = LC_X4_Y4_N5; Fanout = 3; COMB Node = 'Enable_ATA~37'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.200 ns" { EXT_EMIF_MODE Enable_ATA~37 } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 157 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.333 ns) + CELL(2.322 ns) 11.987 ns DC_P3_DETECTn 3 PIN PIN_82 0 " "Info: 3: + IC(3.333 ns) + CELL(2.322 ns) = 11.987 ns; Loc. = PIN_82; Fanout = 0; PIN Node = 'DC_P3_DETECTn'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.655 ns" { Enable_ATA~37 DC_P3_DETECTn } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.368 ns ( 36.44 % ) " "Info: Total cell delay = 4.368 ns ( 36.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.619 ns ( 63.56 % ) " "Info: Total interconnect delay = 7.619 ns ( 63.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.987 ns" { EXT_EMIF_MODE Enable_ATA~37 DC_P3_DETECTn } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.987 ns" { EXT_EMIF_MODE {} EXT_EMIF_MODE~combout {} Enable_ATA~37 {} DC_P3_DETECTn {} } { 0.000ns 0.000ns 4.286ns 3.333ns } { 0.000ns 1.132ns 0.914ns 2.322ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "sync_scl\[0\] PIN_I2C_SCL CLKIN -2.037 ns register " "Info: th for register \"sync_scl\[0\]\" (data pin = \"PIN_I2C_SCL\", clock pin = \"CLKIN\") is -2.037 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN destination 3.458 ns + Longest register " "Info: + Longest clock path from clock \"CLKIN\" to destination register is 3.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLKIN 1 CLK PIN_62 45 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 45; CLK Node = 'CLKIN'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLKIN } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 102 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(0.918 ns) 3.458 ns sync_scl\[0\] 2 REG LC_X2_Y3_N5 1 " "Info: 2: + IC(1.377 ns) + CELL(0.918 ns) = 3.458 ns; Loc. = LC_X2_Y3_N5; Fanout = 1; REG Node = 'sync_scl\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.295 ns" { CLKIN sync_scl[0] } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 502 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 60.18 % ) " "Info: Total cell delay = 2.081 ns ( 60.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.377 ns ( 39.82 % ) " "Info: Total interconnect delay = 1.377 ns ( 39.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLKIN sync_scl[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLKIN {} CLKIN~combout {} sync_scl[0] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 502 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.716 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.716 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PIN_I2C_SCL 1 PIN PIN_98 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_98; Fanout = 1; PIN Node = 'PIN_I2C_SCL'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PIN_I2C_SCL } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns PIN_I2C_SCL~1 2 COMB IOC_X2_Y5_N0 1 " "Info: 2: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = IOC_X2_Y5_N0; Fanout = 1; COMB Node = 'PIN_I2C_SCL~1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.132 ns" { PIN_I2C_SCL PIN_I2C_SCL~1 } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.304 ns) + CELL(0.280 ns) 5.716 ns sync_scl\[0\] 3 REG LC_X2_Y3_N5 1 " "Info: 3: + IC(4.304 ns) + CELL(0.280 ns) = 5.716 ns; Loc. = LC_X2_Y3_N5; Fanout = 1; REG Node = 'sync_scl\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.584 ns" { PIN_I2C_SCL~1 sync_scl[0] } "NODE_NAME" } } { "davincihd.vhd" "" { Text "C:/fpga/davincihd_reve_ver5/davincihd.vhd" 502 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns ( 24.70 % ) " "Info: Total cell delay = 1.412 ns ( 24.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.304 ns ( 75.30 % ) " "Info: Total interconnect delay = 4.304 ns ( 75.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.716 ns" { PIN_I2C_SCL PIN_I2C_SCL~1 sync_scl[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.716 ns" { PIN_I2C_SCL {} PIN_I2C_SCL~1 {} sync_scl[0] {} } { 0.000ns 0.000ns 4.304ns } { 0.000ns 1.132ns 0.280ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.458 ns" { CLKIN sync_scl[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.458 ns" { CLKIN {} CLKIN~combout {} sync_scl[0] {} } { 0.000ns 0.000ns 1.377ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.716 ns" { PIN_I2C_SCL PIN_I2C_SCL~1 sync_scl[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.716 ns" { PIN_I2C_SCL {} PIN_I2C_SCL~1 {} sync_scl[0] {} } { 0.000ns 0.000ns 4.304ns } { 0.000ns 1.132ns 0.280ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}