davincihd.map.rpt

DaVinci HD CPLD Firmware Resources 这是TI原装开发板DM6467原理图的 CPLD的VHDL代码

; Logic element usage by number of LUT inputs ;             ;
;     -- 4 input functions                    ; 49          ;
;     -- 3 input functions                    ; 27          ;
;     -- 2 input functions                    ; 44          ;
;     -- 1 input functions                    ; 8           ;
;     -- 0 input functions                    ; 4           ;
;                                             ;             ;
; Logic elements by mode                      ;             ;
;     -- normal mode                          ; 170         ;
;     -- arithmetic mode                      ; 18          ;
;     -- qfbk mode                            ; 0           ;
;     -- register cascade mode                ; 0           ;
;     -- synchronous clear/load mode          ; 0           ;
;     -- asynchronous clear/load mode         ; 100         ;
;                                             ;             ;
; Total registers                             ; 103         ;
; Total logic cells in carry chains           ; 20          ;
; I/O pins                                    ; 63          ;
; Maximum fan-out node                        ; sync_scl[3] ;
; Maximum fan-out                             ; 59          ;
; Total fan-out                               ; 721         ;
; Average fan-out                             ; 2.87        ;
+---------------------------------------------+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                           ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name        ; Library Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------+--------------+
; |davincihd                 ; 188 (157)   ; 103          ; 0           ; 0            ; 0       ; 0         ; 0         ; 63   ; 0            ; 85 (72)      ; 56 (48)           ; 47 (37)          ; 20 (11)         ; 0 (0)      ; |davincihd                 ; work         ;
;    |davincihdcir:U1|       ; 31 (31)     ; 18           ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; 13 (13)      ; 8 (8)             ; 10 (10)          ; 9 (9)           ; 0 (0)      ; |davincihd|davincihdcir:U1 ; work         ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+-------------------------------------------+
; State Machine - |davincihd|STATE          ;
+----------+----------+----------+----------+
; Name     ; STATE.s2 ; STATE.s1 ; STATE.s0 ;
+----------+----------+----------+----------+
; STATE.s0 ; 0        ; 0        ; 0        ;
; STATE.s1 ; 0        ; 1        ; 1        ;
; STATE.s2 ; 1        ; 0        ; 1        ;
+----------+----------+----------+----------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 103   ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 100   ;
; Number of registers using Asynchronous Load  ; 8     ;
; Number of registers using Clock Enable       ; 40    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; Reg0[0]                                ; 2       ;
; tc_sync_pb_porz[1]                     ; 6       ;
; Reg0[1]                                ; 4       ;
; tc_sync_pb_porz[0]                     ; 2       ;
; DATA_IN_BUF[1]                         ; 3       ;
; ADDR_IN_BUF[1]                         ; 4       ;
; Total number of inverted registers = 6 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (No Restructuring Performed)                                                                        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |davincihd|RIGHT_ADDR      ;
; 4:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |davincihd|DATA_OUT_BUF~26 ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |davincihd|DATA_OUT_BUF~30 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version
    Info: Processing started: Wed Apr 09 07:32:40 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off davincihd -c davincihd
Info: Found 2 design units, including 1 entities, in source file davincihdcir.vhd
    Info: Found design unit 1: davincihdcir-behavior_davincihdcir
    Info: Found entity 1: davincihdcir
Info: Found 2 design units, including 1 entities, in source file davincihd.vhd
    Info: Found design unit 1: davincihd-behavior_davincihd
    Info: Found entity 1: davincihd
Info: Elaborating entity "davincihd" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at davincihd.vhd(236): object "CirSample" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at davincihd.vhd(237): object "CirRise" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at davincihd.vhd(238): object "CirFall" assigned a value but never read
Info: Elaborating entity "davincihdcir" for hierarchy "davincihdcir:U1"
Info: State machine "|davincihd|STATE" contains 3 states
Info: Selected Auto state machine encoding method for state machine "|davincihd|STATE"
Info: Encoding result for state machine "|davincihd|STATE"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "STATE.s2"
        Info: Encoded state bit "STATE.s1"
        Info: Encoded state bit "STATE.s0"
    Info: State "|davincihd|STATE.s0" uses code string "000"
    Info: State "|davincihd|STATE.s1" uses code string "011"
    Info: State "|davincihd|STATE.s2" uses code string "101"
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus HDD_PWR_EN~0 that it feeds
Warning: TRI or OPNDRN buffers permanently enabled
    Warning: Node "HDD_PWR_EN~1"
Info: Registers with preset signals will power-up high
Warning: Design contains 2 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "GP02"
    Warning (15610): No output dependent on input pin "GP03"
Info: Implemented 251 device resources after synthesis - the final resource count might be different
    Info: Implemented 24 input pins
    Info: Implemented 36 output pins
    Info: Implemented 3 bidirectional pins
    Info: Implemented 188 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings
    Info: Allocated 159 megabytes of memory during processing
    Info: Processing ended: Wed Apr 09 07:32:42 2008
    Info: Elapsed time: 00:00:02