📄 davincihd.vhd.bak
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sync_scl <= "0000"; elsif ( CLKIN'event and CLKIN = '1' ) then sync_scl(0) <= PIN_I2C_SCL; sync_scl(1) <= sync_scl(0); sync_scl(2) <= sync_scl(1); if ( sync_scl(2) = sync_scl(1) ) then sync_scl(3) <= sync_scl(2); end if; end if; end process; -- Sync to falling edge of clock process ( Reset_SYSTEM, CLKIN, PIN_I2C_SDA_IN ) begin if ( Reset_SYSTEM = '1' ) then sync_sda <= "0000"; elsif ( CLKIN'event and CLKIN = '0' ) then sync_sda(0) <= PIN_I2C_SDA_IN; sync_sda(1) <= sync_sda(0); sync_sda(2) <= sync_sda(1); if ( sync_sda(2) = sync_sda(1) ) then sync_sda(3) <= sync_sda(2); end if; end if; end process; -- I2C signals are Sync to clock I2C_SCL <= sync_scl(3); I2C_SDA_IN <= sync_sda(3); process ( Reset_SYSTEM, STATE, I2C_SCL, START, STOP, RIGHT_ADDR, WRONG_ADDR, DATA_READ, DATA_WRITE ) begin if ( Reset_SYSTEM = '1' ) then STATE <= s0; elsif ( I2C_SCL = '0' and I2C_SCL'event ) then case STATE is when s0 => if ( START = '1' ) then STATE <= s1; else STATE <= s0; end if; when s1 => if ( RIGHT_ADDR = '1' ) then STATE <= s2; elsif ( WRONG_ADDR = '1' ) then STATE <= s0; else STATE <= s1; end if; when s2 => if ( DATA_ACK = '1' or DATA_WRITE = '1' or STOP = '1' ) then STATE <= s0; else STATE <= s2; end if; end case; end if; end process; ----------------------------------------------------------------------------- -- Start condition detection process ( STATE, I2C_SCL, I2C_SDA_IN ) begin if ( I2C_SCL = '1' ) then if ( I2C_SDA_IN = '0' and I2C_SDA_IN'event ) then START <= '1'; end if; else START <= '0'; end if; end process; ----------------------------------------------------------------------------- -- Stop condition detection process( STATE, I2C_SCL, I2C_SDA_IN ) begin if ( I2C_SCL = '1' ) then if ( I2C_SDA_IN = '1' and I2C_SDA_IN'event ) then if ( STATE = s0 ) then STOP <= '0'; else STOP <= '1'; end if; end if; else STOP <= '0'; end if; end process; ------------------------------------------------------------------------------ -- ACK Back & Send DATA Out I2C_SDA_OUT <= '0' when ( Reset_SYSTEM = '0' ) -- Not in Reset and ( ADDR_ACK = '1' -- Ack to Address or DATA_ACK = '1' -- Ack to 8-bit Data Write or DATA_OUT = '0' ) -- Output of Data Read else 'Z'; ------------------------------------------------------------------------------ -- Shift in Address process ( STATE, I2C_SCL, I2C_SDA_IN, ADDR_IN_BUF ) begin if ( STATE = s1 ) then if ( I2C_SCL = '1' and I2C_SCL'event ) then ADDR_IN_BUF(9 downto 0) <= ADDR_IN_BUF(8 downto 0) & I2C_SDA_IN; end if; else ADDR_IN_BUF <= "0000000010"; -- Built in Counter at index [0] end if; end process; ------------------------------------------------------------------------------ -- Check Address process ( STATE, I2C_SCL, ADDR_IN_BUF ) begin if ( STATE = s1 ) then if ( I2C_SCL = '0' and I2C_SCL'event and ADDR_IN_BUF(9) = '1' ) then -- 0x3A if ( ADDR_IN_BUF(7 downto 1) = "0111010" ) then -- Right Address RIGHT_ADDR <= '1'; ADDR_ACK <= '1'; -- Store Reg address & Data direction REG_ADDR <= "00"; READ_OR_WRITE <= ADDR_IN_BUF(0); -- 0x3B elsif ( ADDR_IN_BUF(7 downto 1) = "0111011" ) then RIGHT_ADDR <= '1'; ADDR_ACK <= '1'; -- Store Reg address & Data direction REG_ADDR <= "01"; READ_OR_WRITE <= ADDR_IN_BUF(0); -- 0x3C elsif ( ADDR_IN_BUF(7 downto 1) = "0111100" ) then RIGHT_ADDR <= '1'; ADDR_ACK <= '1'; -- Store Reg address & Data direction REG_ADDR <= "10"; READ_OR_WRITE <= ADDR_IN_BUF(0); else -- Wrong Address WRONG_ADDR <= '1'; ADDR_ACK <= '0'; end if; end if; else ADDR_ACK <= '0'; RIGHT_ADDR <= '0'; WRONG_ADDR <= '0'; end if; end process; ------------------------------------------------------------------------------ -- Shift in Data process ( STATE, I2C_SCL, I2C_SDA_IN, DATA_IN_BUF ) begin if ( STATE = s2 ) then if ( I2C_SCL = '1' and I2C_SCL'event ) then DATA_IN_BUF(9 downto 0) <= DATA_IN_BUF(8 downto 0) & I2C_SDA_IN; end if; else DATA_IN_BUF <= "0000000010"; -- Built in Counter at index [0] end if; end process; ------------------------------------------------------------------------------ -- Shift out Data process ( STATE, I2C_SCL, I2C_SDA_IN, RIGHT_ADDR, READ_OR_WRITE, REG_ADDR, DATA_OUT_BUF, Reg0, Reg1 ) begin if ( STATE = s0 ) then DATA_OUT_BUF <= "11111111"; elsif ( STATE = s1 ) then if ( RIGHT_ADDR = '1' and READ_OR_WRITE = '1' ) then if ( REG_ADDR = "00" ) then DATA_OUT_BUF <= Reg0; elsif ( REG_ADDR = "01" ) then DATA_OUT_BUF <= Reg1; elsif ( REG_ADDR = "10" ) then DATA_OUT_BUF <= "00000110"; -- Reg2 = 6; else DATA_OUT_BUF <= "00000000"; end if; end if; elsif ( STATE = s2 ) then if ( I2C_SCL = '0' and I2C_SCL'event and READ_OR_WRITE = '1' ) then DATA_OUT_BUF <= DATA_OUT_BUF(6 downto 0) & '1'; end if; end if; end process; DATA_OUT <= DATA_OUT_BUF(7); ------------------------------------------------------------------------------ -- Send Ack & Data process ( STATE, I2C_SCL, DATA_IN_BUF ) begin if ( STATE = s2 ) then if ( I2C_SCL = '0' and I2C_SCL'event ) then -- Write [to Own Register] if ( READ_OR_WRITE = '0' ) then if ( DATA_IN_BUF(8) = '1' ) then DATA_READ <= '1'; DATA_ACK <= '0'; elsif ( DATA_IN_BUF(9) = '1' ) then DATA_READ <= '0'; DATA_ACK <= '1'; end if; -- Read [from Own Register] elsif ( READ_OR_WRITE = '1' ) then DATA_ACK <= '0'; if ( DATA_IN_BUF(8) = '1' ) then DATA_WRITE <= '1'; end if; end if; end if; else DATA_ACK <= '0'; DATA_READ <= '0'; DATA_WRITE <= '0'; end if; end process; ------------------------------------------------------------------------------ -- SAVE DATA process ( Reset_SYSTEM, STATE, I2C_SCL, STOP, DATA_IN_BUF, REG_ADDR, DATA_READ ) begin if ( Reset_SYSTEM = '1' ) then Reg0 <= "00000011";
--Reg0 <= "00000000";
Reg1 <= "00000000"; else if ( I2C_SCL = '0' and I2C_SCL'event and DATA_READ = '1' ) then if ( REG_ADDR = "00" ) then Reg0 <= DATA_IN_BUF(7 downto 0); elsif ( REG_ADDR = "01" ) then Reg1 <= DATA_IN_BUF(7 downto 0); end if; end if; end if; end process;end behavior_davincihd;
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