📄 davincihd.vhd.bak
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( Reset_SYSTEM=> Reset_SYSTEM, CLKIN => CLKIN, CIRIN => CirIn, CIROUT => CirOut, CIRSAMPLE => CirSample, CIRRISE => CirRise, CIRFALL => CirFall );
-- Create a 8 bit counter that we can use for doing some
-- button filtering
process( POR_RESETn, CLKIN, PB_RESET) begin
if POR_RESETn = '0' or PB_RESET = '1' then
tc_ponrs_counter <= (others => '0');
elsif CLKIN'event and CLKIN = '1' then
tc_ponrs_counter <= tc_ponrs_counter + 1; end if;
end process;
-- Create capture signal every 512 clocks
process( POR_RESETn, CLKIN, tc_ponrs_counter )
begin
if POR_RESETn = '0' then
tc_sync_pb_capture <= '0';
elsif CLKIN'event and CLKIN = '1' then
if( tc_ponrs_counter = "111111111111" ) then tc_sync_pb_capture <= '1';
else
tc_sync_pb_capture <= '0';
end if;
end if;
end process;
-- PB reset is high for reset
process( POR_RESETn, CLKIN, tc_sync_pb_capture, PB_RESET )
begin
if POR_RESETn = '0' or PB_RESET = '1' then
tc_sync_pb_porz <= "11";
elsif CLKIN'event and CLKIN = '1' then
if( tc_sync_pb_capture = '1' ) then
tc_sync_pb_porz(0) <= '0';
tc_sync_pb_porz(1) <= tc_sync_pb_porz(0);
end if;
end if;
end process;
process( POR_RESETn, CLKIN, tc_sync_pb_capture )
begin
if POR_RESETn = '0' then
tc_sync_ponrs <= "000";
elsif CLKIN'event and CLKIN = '1' then
if( tc_sync_pb_capture = '1' ) then
tc_sync_ponrs(0) <= '1';
tc_sync_ponrs(1) <= tc_sync_ponrs(0);
tc_sync_ponrs(2) <= tc_sync_ponrs(1);
end if;
end if;
end process;
process( POR_RESETn, CLKIN, tc_ponrs_counter , tc_sync_ponrs )
begin
if POR_RESETn = '0' then
tc_scl_low <= '0';
elsif CLKIN'event and CLKIN = '1' then
if( ( tc_sync_ponrs(0) = '0' ) or (tc_sync_pb_porz(0) = '1' ))then
if( ( tc_ponrs_counter(8 downto 5) = "0001" )
or ( tc_ponrs_counter(8 downto 5) = "0011" )
or ( tc_ponrs_counter(8 downto 5) = "0101" )
or ( tc_ponrs_counter(8 downto 5) = "0111" )
or ( tc_ponrs_counter(8 downto 5) = "1001" )
or ( tc_ponrs_counter(8 downto 5) = "1011" )
or ( tc_ponrs_counter(8 downto 5) = "1101" )
or ( tc_ponrs_counter(8 downto 5) = "1111" ) )then
tc_scl_low <= '0';
else
tc_scl_low <= '1';
end if;
else
tc_scl_low <= '1';
end if;
end if;
end process;
------------------------------------------------------------------------ -- System Resets --Reset_POR <= '1' when POR_RESETn = '0' else '0'; -- PowerOnReset --Reset_PB <= '1' when PB_RESET = '1' else '0'; -- PushButtonReset
Reset_POR <= '1' when tc_sync_ponrs(2) = '0' else '0'; -- PowerOnReset
Reset_PB <= '1' when tc_sync_pb_porz(1) = '1' else '0'; -- PushButtonReset
-- Control Logic: Global Resets
Reset_SYSTEM <= '1' when Reset_PB = '1' or Reset_POR = '1' else '0'; Reset_CPU <= '1' when Reset_PB = '1' or ARM_EMU_RSTn = '0' else '0';
-- Control Logic: Peripheral Resets Reset_ATA <= '1' when Reset_SYSTEM = '1' or Reg0(0) = '1' else '0'; Reset_VLYNQ <= '1' when Reset_SYSTEM = '1' or Reg0(3) = '1' else '0'; Reset_TVP5147 <= '1' when Reset_SYSTEM = '1' or Reg1(0) = '1' else '0'; Reset_TVP7002 <= '1' when Reset_SYSTEM = '1' or Reg1(2) = '1' else '0'; -- Pin Control: SYS_RESETn <= '0' when Reset_SYSTEM = '1' else '1'; CPU_RESETz <= '0' when Reset_CPU = '1' else '1'; CPU_PORz <= '0' when Reset_POR = '1' else '1'; ATA_RESETn <= '0' when Reset_ATA = '1' else '1'; VLYNQ_RESETn <= '0' when Reset_VLYNQ = '1' else '1'; TVP5147_RSTn <= '0' when Reset_TVP5147= '1' else '1'; TVP7002_RSTn <= '0' when Reset_TVP7002= '1' else '1'; --PIN_I2C_SCL <= '0' when Reset_PB = '1' else 'Z';
PIN_I2C_SCL <= '0' when tc_scl_low = '0' else 'Z';
------------------------------------------------------------------------ -- ATA/PCI/DC_P3 -- Control Logic: NAND Enable_NAND <= '1' when PCI_DETECTn = '1' -- No PCI and EXT_EMIF_MODE = '0' -- No External EMIF else '0'; -- Control Logic: ATA Enable_ATA_PWR <= '1' when Reg0(1) = '0' else '0'; -- ATA Power +5V Enable_ATA <= '1' when PCI_DETECTn = '1' -- No PCI and EXT_EMIF_MODE = '0' -- No External EMIF --and ATA_BUFF_PWR = '1' -- ATA Power On
and Reg0(1) = '0' else '0'; -- Control Logic: PCI Enable_PCI <= '1' when PCI_DETECTn = '0' else '0'; -- Control Logic: External EMIF [DC_P3] Enable_EXT_EMIF <= '1' when EXT_EMIF_MODE = '1' else '0'; -- Pin Control: ATA/PCI/DC_P3 [only 1 active] PCI_DETECTS0 <= '1' when Enable_PCI = '1' or Enable_EXT_EMIF = '1' else '0'; PCI_DETECTS1 <= '1' when Enable_ATA = '1' or Enable_NAND = '1' else '0'; PCI_DETECTS2 <= '1' when Enable_EXT_EMIF = '1' else '0'; -- Pin Control: ATA HDD_PWR_EN <= 'Z' when Enable_ATA_PWR = '1' else '0'; -- ATA +5V ATA_CTL_BUFF_ONn <= '0' when Enable_ATA = '1' else '1'; -- ATA.[CTRLs] ATA_DATA_BUFF_ONn <= '0' when Enable_ATA = '1' else '1'; -- ATA.D[15:0] DC_P3_DETECTn <= '1' when Enable_ATA = '1' else '0'; -- ATA.DA[1:0] PCI_ATA_DETECTn <= '0' when Enable_ATA = '1' -- ATA.DA2 or Enable_EXT_EMIF = '1' else '1'; -- EM.A22/GPIO13 -- Pin Control: PCI CTL_PCI_DETECTn <= '0' when Enable_PCI = '1' else '1'; -- PCI.RSTn PCI_FORCE_ON <= '0' when Enable_PCI = '1' else '1'; -- PCIEN ------------------------------------------------------------------------ -- I2C GPIO Interrupt GP00 <= I2C_INTn when Reg0(6) = '0' else '1'; ------------------------------------------------------------------------ -- POWER (1.2V CORE) VSCALE0 <= GP06 when Reg0(2) = '1' else '1'; -- VDDADJ0 VSCALE1 <= GP07 when Reg0(2) = '1' else '1'; -- VDDADJ1 ------------------------------------------------------------------------ -- USB +5V POWER DRV_VBUS <= 'Z' when USB_VBUS = '1' else '0'; GP04 <= VBUS_FEEDBACK when Reg0(7) = '0' else '0'; ------------------------------------------------------------------------ -- External DC_P3 VCXO CPLD_DC_ALT_VCXO_ENn <= '0' when DC_ALT_VCXO_EN = '1' else '1'; -- INPUT: DC_ALT_VCXO CPLD_DC_VCXO_CLK_ENn <= '0' when DC_VCXO_CLK_EN = '1' else '1'; -- OUTPUT: DC_VCXO_CLK ------------------------------------------------------------------------ -- Video Decoder [INPUT] -- Control Logic Enable_CV <= '1' when Reg1(5) = '0' and VIDEO_IN_EN0 = '0' else '0'; Enable_SV <= '1' when Reg1(5) = '0' and VIDEO_IN_EN1 = '0' else '0'; Enable_HD_Y <= '1' when Reg1(5) = '1' and VIDEO_IN_EN0 = '0' else '0'; Enable_HD_C <= '1' when Reg1(5) = '1' and VIDEO_IN_EN1 = '0' else '0'; -- Pin Control VID_INLO_S0 <= '1' when Enable_CV = '1' else '0'; -- CV VID_INLO_S1 <= '1' when Enable_HD_Y = '1' else '0'; -- HD_Y VID_INHI_S0 <= '1' when Enable_SV = '1' else '0'; -- SV VID_INHI_S1 <= '1' when Enable_HD_C = '1' else '0'; -- HD_C TVP5147_PWD <= '1' when Reg1(1) = '1' else '0'; -- CV/SV TVP7002_PWD <= '1' when Reg1(3) = '1' else '0'; -- HD_Y/HD_C TVP5417_I2Cn <= '0' when Reg1(4) = '0' else '1'; -- [U34]:TVP5147_1 TVP7002_I2Cn <= '0' when Reg1(4) = '1' else '1'; -- [U7] :TVP7002 ------------------------------------------------------------------------ -- Video Encoder [OUTPUT] -- Control Logic Enable_ADV_S <= '1' when Reg1(6) = '0' and VIDEO_OUT_EN0 = '0' else '0'; -- SD:YCrCb Enable_ADV_Y <= '1' when Reg1(6) = '1' and VIDEO_OUT_EN0 = '0' else '0'; -- HD:Y Enable_ADV_C <= '1' when Reg1(6) = '1' and VIDEO_OUT_EN1 = '0' else '0'; -- HD:CrCb -- Pin Control VIDOUT_LO_S0 <= '1' when Enable_ADV_S = '1' else '0'; -- SD:YCrCb VIDOUT_LO_S1 <= '1' when Enable_ADV_Y = '1' else '0'; -- HD:Y VIDOUT_HI_S0 <= '0' when Enable_ADV_C = '1' else '1'; -- HD:CrCb ------------------------------------------------------------------------------ -- CIR -- Control Logic [DeModulated CIR] Enable_DEMODULATED_CIR <= '1' when Reg0(4) = '0' and GPIO_IR_EN = '0' else '0'; -- Pin Control [DeModulated CIR] GP01 <= IR_IN when Enable_DEMODULATED_CIR = '1' else 'Z'; -- Control Logic [36 KHz Modulated CIR] Enable_MODULATED_CIR <= '1' when Reg0(5) = '0' and UART2_EN = '0' else '0'; -- Pin Control [36 KHz Modulated CIR] UART2_RXD <= CirOut when Enable_MODULATED_CIR = '1' else 'Z'; CirIn <= not IR_IN when Enable_MODULATED_CIR = '1' else '0'; ------------------------------------------------------------------------------ -- I2C ------------------------------------------------------------------------------ ------------------------------------------------------------------------------ -- I2C State Machine -- -- State machine, goes from: -- [s0:Idle] -> [s1:Read Address] -> [Ack] -> [s2:Read/Write Data] -> [Ack] -- -- Transitions: -- [START SEQ] s0 -> s1 -- [WRONG_ADDR] s1 -> s0 -- [RIGHT_ADDR] s1 -> s2 -- [DATA_READ] s2 -> s0 -- [DATA_WRITE] s2 -> s0 -- [STOP_SEQ] s2 -> s0 -- ------------------------------------------------------------------------------ -- Sync to rising edge of clock process ( Reset_SYSTEM, CLKIN, PIN_I2C_SCL ) begin if ( Reset_SYSTEM = '1' ) then⌨️ 快捷键说明
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