📄 davincihd.vhd.bak
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---------------------------------------------------------------------------------- $Archive:: /VHDL/product/davincihd/davincihd.vhd $-- $Revision:: 005 $-- $Date:: January 15, 2008 $-- $Author:: davyh $------ Copyright (c) 2007, Spectrum Digital Incorporated-- All rights reserved----------------------------------------------------------------------------------------------------------------------------------------------------------------- Start the real code-------------------------------------------------------------------------------library IEEE;use IEEE.std_logic_1164.all;entity davincihd is port ( UART2_RXD : out std_logic; -- 36 KHz Modulated CIR on UART2.RX [to CPU] UART2_EN : in std_logic; -- 36 KHz Modulated CIR UART2 Enable ATA_RESETn : out std_logic; -- ATA Reset ATA_CTL_BUFF_ONn : out std_logic; -- ATA Control Buffer ATA_DATA_BUFF_ONn : out std_logic; -- ATA Data Buffer ATA_BUFF_PWR : in std_logic; -- ATA +5V feedback GP00 : out std_logic; -- I2C GPIO INTn [to CPU] GP01 : out std_logic; -- CIR Data [to CPU] GP02 : in std_logic; -- GP03 : in std_logic; -- GP04 : out std_logic; -- USB.VBUS [to CPU] GP06 : in std_logic; -- CPU.VDDADJ0 [from CPU] GP07 : in std_logic; -- CPU.VDDADJ1 [from CPU] GPIO_IR_EN : in std_logic; -- DeModulated CIR Enable I2C_INTn : in std_logic; -- I2C GPIO INTn [Need Pullup] ARM_EMU_RSTn : in std_logic; -- 20-pin ARM JTAG Reset PB_RESET : in std_logic; -- Push Button Reset POR_RESETn : in std_logic; -- Power-On-Reset TVP7002_RSTn : out std_logic; -- TVP7002 Reset TVP7002_PWD : out std_logic; -- TVP7002 Powerdown TVP5147_RSTn : out std_logic; -- TVP5147 Reset TVP5147_PWD : out std_logic; -- TVP5147 Powerdown PCI_FORCE_ON : out std_logic; -- PCIEN Bootmode Force HI PCI_DETECTn : in std_logic; -- PCI Plug Detect DC_ALT_VCXO_EN : in std_logic; -- OffBoard Enable DC_P2.46 DC_VCXO_CLK_EN : in std_logic; -- OffBoard Enable DC_P2.45 CPLD_DC_ALT_VCXO_ENn : out std_logic; -- INPUT from DC_P2.48 CPLD_DC_VCXO_CLK_ENn : out std_logic; -- OUTPUT to DC_P2.47 TVP5417_I2Cn : out std_logic; -- Enable TVP5417 I2C TVP7002_I2Cn : out std_logic; -- Enable TVP7002 I2C IR_IN : in std_logic; -- DeModulated CIR VIDEO_IN_EN0 : in std_logic; -- Disable Video Input Circuitry VIDEO_IN_EN1 : in std_logic; -- VIDEO_OUT_EN0 : in std_logic; -- Disable Video Output Circuitry VIDEO_OUT_EN1 : in std_logic; -- [DC_P3] VID_INLO_S0 : out std_logic; -- Video Input Select [CV/HD_Y] VID_INLO_S1 : out std_logic; -- VID_INHI_S0 : out std_logic; -- Video Input Select [SV/HD_C] VID_INHI_S1 : out std_logic; -- VIDOUT_LO_S0 : out std_logic; -- Video Output Select [ADV_S/ADV_Y] VIDOUT_LO_S1 : out std_logic; -- VIDOUT_HI_S0 : out std_logic; -- Video Output Select [ADV_C] SYS_RESETn : out std_logic; -- Global System Reset CPU_RESETz : out std_logic; -- [U1.W6] CPU Reset CPU_PORz : out std_logic; -- [U1.D17] CPU Power-On-Reset VLYNQ_RESETn : out std_logic; -- OnBoard VLYNQ Reset [JP2.3] HDD_PWR_EN : inout std_logic; -- OnBoard HDD +5V Enable DC_P3_DETECTn : out std_logic; -- ATA/DC_P3 select PCI_ATA_DETECTn : out std_logic; -- ATA+DC_P3 select VSCALE0 : out std_logic; -- 1.2V Core Voltage Adjuster VSCALE1 : out std_logic; -- 1.2V Core Voltage Adjuster USB_VBUS : in std_logic; -- OnChip USB +5V Enable DRV_VBUS : inout std_logic; -- OnBoard USB +5V Enable CTL_PCI_DETECTn : out std_logic; -- ATA/DC_P3/PCI select PCI_DETECTS0 : out std_logic; -- PCI/ATA-NAND/DC_P3 Select PCI_DETECTS1 : out std_logic; -- PCI_DETECTS2 : out std_logic; -- VBUS_FEEDBACK : in std_logic; -- +5V USB feedback EXT_EMIF_MODE : in std_logic; -- External EMIF Select CLKIN : in std_logic; -- 12 MHz Clock PIN_I2C_SCL : inout std_logic; -- I2C Clock PIN_I2C_SDA_IN : in std_logic; I2C_SDA_OUT : out std_logic -- I2C Data );end davincihd;--------------------------------------------------------------------------------- Include standard librariess-------------------------------------------------------------------------------library IEEE;use IEEE.std_logic_1164.all;-- use work.std_arith.all;use IEEE.std_logic_arith.all;use IEEE.std_logic_unsigned.all;architecture behavior_davincihd of davincihd is--------------------------------------------------------------------------------- Add local components in here-------------------------------------------------------------------------------component davincihdcirport ( Reset_SYSTEM : in std_logic; CLKIN : in std_logic; CIRIN : in std_logic; CIROUT : out std_logic; CIRSAMPLE : out std_logic; CIRRISE : out std_logic; CIRFALL : out std_logic );end component;--------------------------------------------------------------------------------- Add signals------------------------------------------------------------------------------- ------------------------------------------------------------------------ -- All Reset_##### signals are Active HIGH! This simplifies the logic. ------------------------------------------------------------------------ signal Reset_POR : std_logic; -- Reset [from USER] signal Reset_PB : std_logic; signal Reset_SYSTEM : std_logic; -- Reset [to Individual Parts] signal Reset_ATA : std_logic; signal Reset_CPU : std_logic; signal Reset_TVP5147 : std_logic; signal Reset_TVP7002 : std_logic; signal Reset_VLYNQ : std_logic; ------------------------------------------------------------------------ -- All Enable_##### signals are Active HIGH! This simplifies the logic. ------------------------------------------------------------------------ signal Enable_NAND : std_logic; -- NAND signal Enable_ATA : std_logic; -- ATA signal Enable_ATA_PWR : std_logic; signal Enable_PCI : std_logic; -- PCI signal Enable_EXT_EMIF : std_logic; -- External EMIF signal Enable_CV : std_logic; -- TVP5147.VideoIn signal Enable_SV : std_logic; signal Enable_HD_Y : std_logic; -- TVP7002.VideoIn signal Enable_HD_C : std_logic; signal Enable_ADV_S : std_logic; -- ADV7343.VideoOut signal Enable_ADV_Y : std_logic; signal Enable_ADV_C : std_logic; signal Enable_MODULATED_CIR : std_logic; -- 36 KHz Modulated CIR signal Enable_DEMODULATED_CIR : std_logic; -- DeModulated CIR ------------------------------------------------------------------------ -- I2C ------------------------------------------------------------------------ type STATE_TYPE is ( s0, s1, s2 ); signal STATE : STATE_TYPE; signal START : std_logic; -- Start/Stop Seq signal STOP : std_logic; signal WRONG_ADDR : std_logic; -- Address Check signal RIGHT_ADDR : std_logic; signal ADDR_ACK : std_logic; signal READ_OR_WRITE : std_logic; -- Data & Direction signal REG_ADDR : std_logic_vector(1 downto 0); signal DATA_READ : std_logic; -- Data IN/OUT signal DATA_WRITE : std_logic; signal DATA_ACK : std_logic; signal DATA_OUT : std_logic; signal ADDR_IN_BUF : std_logic_vector(9 downto 0); signal DATA_IN_BUF : std_logic_vector(9 downto 0); signal DATA_OUT_BUF : std_logic_vector(7 downto 0); ------------------------------ Reg0 (0x3a) ----------------------------- -- [=0] [=1] -- BIT 0 ATA_RSTn *ATA Normal ATA Reset -- BIT 1 ATA_PWD *ATA Power +5V ATA Power OFF -- BIT 2 VSCALEON *VSCALE[0:1]=HIGH VSCALE[0:1]=GP[06:07]/VDDADJ[0:1] -- BIT 3 VLYNQ_RSTn *VLYNQ Normal VLYNQ Reset -- BIT 4 CIR_DEMOD *DeModulated CIR=[GP01] DeModulated Disabled -- BIT 5 CIR_MOD *36-KHz CIR=[UART2_RXD] 36-KHz Modulated Disabled -- BIT 6 I2C_INT *I2C INT Enable I2C INT Disable -- BIT 7 USB_FB *USB Feedback Enable USB Feedback Disable ------------------------------------------------------------------------ signal Reg0 : std_logic_vector(7 downto 0); ------------------------------- Reg1 (0x3b) ----------------------------- -- [=0] [=1] -- BIT 0 TVP5147_RST *TVP5147 Normal TVP5147 Reset -- BIT 1 TVP5147_PWD *TVP5147 Normal Mode TVP5147 Power Down -- BIT 2 TVP7002_RST *TVP7002 Normal TVP7002 Reset -- BIT 3 TVP7002_PWD *TVP7002 Normal Mode TVP7002 Power Down -- BIT 4 TVP_SELECT *Select TVP5147 Select TVP7002 -- BIT 5 VID_IN_MODE *Standard Def In High Def In -- (CV/SV) (HD_Y/HD_C) -- BIT 6 VID_OUT_MODE *Standard Def Out High Def Out -- (ADV_S) (ADV_Y/ADV_C) -- BIT 7 - ------------------------------------------------------------------------ signal Reg1 : std_logic_vector(7 downto 0); ------------------------------ Reg2 (0x3c) ----------------------------- -- BIT [7:0] Version ID = 6 ------------------------------------------------------------------------ -- Constant, Read Only signal I2C_SCL : std_logic; signal I2C_SDA_IN : std_logic; signal sync_sda : std_logic_vector( 3 downto 0 ); signal sync_scl : std_logic_vector( 3 downto 0 ); signal CirIn : std_logic; signal CirOut : std_logic; signal CirSample : std_logic; signal CirRise : std_logic; signal CirFall : std_logic;
signal tc_ponrs_counter : std_logic_vector( 11 downto 0); signal tc_sync_ponrs : std_logic_vector(2 downto 0);
signal tc_sync_pb_porz : std_logic_vector(1 downto 0);
signal tc_sync_pb_capture : std_logic;
signal tc_scl_low : std_logic;
--------------------------------------------------------------------------------- The implementation-------------------------------------------------------------------------------begin U1: davincihdcir port map⌨️ 快捷键说明
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