davincihdcir.vhd

DaVinci HD CPLD Firmware Resources 这是TI原装开发板DM6467原理图的 CPLD的VHDL代码

--------------------------------------------------------------------------------
-- $Archive:: /VHDL/product/davincihd/davincihd.vhd                            $
-- $Revision:: 004                                                             $
-- $Date:: August 22, 2007                                                     $
-- $Author:: davyh                                                             $
--
--
-- Copyright (c) 2007, Spectrum Digital Incorporated
-- All rights reserved
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start the real code
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity davincihdcir is
  port
  (
    Reset_SYSTEM        : in  std_logic;
    CLKIN               : in  std_logic;
    CIRIN               : in  std_logic;
    CIROUT              : out std_logic;
    CIRSAMPLE           : out std_logic;
    CIRRISE             : out std_logic;
    CIRFALL             : out std_logic
  );
end davincihdcir;

-------------------------------------------------------------------------------
-- Include standard librariess
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- use work.std_arith.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

architecture behavior_davincihdcir of davincihdcir is

-------------------------------------------------------------------------------
-- Add local components in here
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
-- Add signals
-------------------------------------------------------------------------------
  signal clkdiv       : std_logic_vector( 8 downto 0 );
  signal clken        : std_logic;
  signal sync         : std_logic_vector( 3 downto 0 );
  signal risingedge   : std_logic;
  signal fallingedge  : std_logic;

  signal modulate     : std_logic;
  signal cirmod       : std_logic;
  signal cirinsync    : std_logic;

-------------------------------------------------------------------------------
-- The implementation
-------------------------------------------------------------------------------
begin
    process( Reset_SYSTEM, CLKIN )
    begin
        if ( Reset_SYSTEM = '1' ) then
            clkdiv <= "000000000";
            clken  <= '0';
        elsif ( CLKIN'event and CLKIN = '1' ) then
            if( clkdiv = "000000000" ) then
                clken <= '1';
            else
                clken <= '0';
            end if;

            if ( clkdiv = "010101000" ) then -- 0xA8 (167+1)
                clkdiv <= "000000000";
            else
                clkdiv <= clkdiv + "000000001";
            end if;
        end if;
    end process;

    process( Reset_SYSTEM, CLKIN, CIRIN )
    begin
        if ( Reset_SYSTEM = '1' ) then
            sync <= "0000";
        elsif ( CLKIN'event and CLKIN = '1' ) then
            if ( clken = '1' ) then
                sync( 3 downto 0 ) <= sync( 2 downto 0 ) & CIRIN;
            end if;
        end if;
    end process;

    process( Reset_SYSTEM, CLKIN, sync )
    begin
        if ( Reset_SYSTEM = '1' ) then
            risingedge <= '0';
        elsif ( CLKIN'event and CLKIN = '1' ) then
            if ( clken = '1' ) then
                if ( sync = "0111" ) then
                    risingedge <= '1';
                else
                    risingedge <= '0';
                end if;
            end if;
        end if;
    end process;

    process( Reset_SYSTEM, CLKIN, sync )
    begin
        if ( Reset_SYSTEM = '1' ) then
            fallingedge <= '0';
        elsif ( CLKIN'event and CLKIN = '1' ) then
            if( clken = '1' ) then
                if( sync = "1000" ) then
                    fallingedge <= '1';
                else
                    fallingedge <= '0';
                end if;
            end if;
        end if;
    end process;

    process( Reset_SYSTEM, CLKIN, risingedge, fallingedge )
    begin
        if ( Reset_SYSTEM = '1' ) then
            modulate <= '0';
        elsif ( CLKIN'event and CLKIN = '1' ) then
            if ( clken = '1' ) then
                if ( risingedge = '1' ) then
                    modulate <= '1';
                elsif ( fallingedge = '1' ) then
                    modulate <= '0';
                end if;
            end if;
        end if;
    end process;

    process( Reset_SYSTEM, CLKIN, modulate )
    begin
        if ( Reset_SYSTEM = '1' ) then
            cirmod <= '0';
        elsif ( CLKIN'event and CLKIN = '1' ) then
            if ( clken = '1' ) then
                cirmod <= not cirmod and modulate;
            end if;
        end if;
    end process;

    CIROUT      <= cirmod;
    CIRSAMPLE   <= clken;
    CIRRISE     <= risingedge;
    CIRFALL     <= fallingedge;

end behavior_davincihdcir;