davincihd.tan.summary

DaVinci HD CPLD Firmware Resources 这是TI原装开发板DM6467原理图的 CPLD的VHDL代码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.897 ns
From           : IR_IN
To             : davincihdcir:U1|sync[0]
From Clock     : --
To Clock       : CLKIN
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 15.667 ns
From           : Reg1[5]
To             : VID_INHI_S1
From Clock     : CLKIN
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 11.987 ns
From           : EXT_EMIF_MODE
To             : DC_P3_DETECTn
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.037 ns
From           : PIN_I2C_SCL
To             : sync_scl[0]
From Clock     : --
To Clock       : CLKIN
Failed Paths   : 0

Type           : Clock Setup: 'CLKIN'
Slack          : 35.428 ns
Required Time  : 12.00 MHz ( period = 83.333 ns )
Actual Time    : 80.14 MHz ( period = 12.478 ns )
From           : Reg0[5]
To             : davincihdcir:U1|sync[0]
From Clock     : CLKIN
To Clock       : CLKIN
Failed Paths   : 0

Type           : Clock Hold: 'CLKIN'
Slack          : 1.377 ns
Required Time  : 12.00 MHz ( period = 83.333 ns )
Actual Time    : N/A
From           : tc_sync_ponrs[1]
To             : tc_sync_ponrs[2]
From Clock     : CLKIN
To Clock       : CLKIN
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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