h_adder.vhd

来自「全加器」· VHDL 代码 · 共 23 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY h_adder IS
	PORT
	(
		a,b		: IN	STD_LOGIC;
		co,so	: OUT	STD_LOGIC
	);
END h_adder;
ARCHITECTURE fh1 OF h_adder IS
SIGNAL abc:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
	abc<=a&b;
	PROCESS(abc)
	BEGIN
	CASE abc IS
	WHEN "00"=> SO<='0'; co<='0';
	WHEN "01"=> SO<='1'; co<='0';
	WHEN "10"=> SO<='1'; co<='0';
	WHEN "11"=> SO<='1'; co<='1';
	END CASE;
	END PROCESS;
END ;