f_adder.map.qmsg

全加器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 02 19:25:47 2008 " "Info: Processing started: Sun Nov 02 19:25:47 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off f_adder -c f_adder " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off f_adder -c f_adder" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f_adder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file f_adder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 f_adder-fd1 " "Info: Found design unit 1: f_adder-fd1" {  } { { "f_adder.vhd" "" { Text "D:/Quatus2/works/summrize/f_adder/f_adder.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 f_adder " "Info: Found entity 1: f_adder" {  } { { "f_adder.vhd" "" { Text "D:/Quatus2/works/summrize/f_adder/f_adder.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "h_adder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file h_adder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 h_adder-fh1 " "Info: Found design unit 1: h_adder-fh1" {  } { { "h_adder.vhd" "" { Text "D:/Quatus2/works/summrize/f_adder/h_adder.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 h_adder " "Info: Found entity 1: h_adder" {  } { { "h_adder.vhd" "" { Text "D:/Quatus2/works/summrize/f_adder/h_adder.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "or2a.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file or2a.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 or2a-a " "Info: Found design unit 1: or2a-a" {  } { { "or2a.vhd" "" { Text "D:/Quatus2/works/summrize/f_adder/or2a.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 or2a " "Info: Found entity 1: or2a" {  } { { "or2a.vhd" "" { Text "D:/Quatus2/works/summrize/f_adder/or2a.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "f_adder " "Info: Elaborating entity \"f_adder\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "h_adder h_adder:u1 " "Info: Elaborating entity \"h_adder\" for hierarchy \"h_adder:u1\"" {  } { { "f_adder.vhd" "u1" { Text "D:/Quatus2/works/summrize/f_adder/f_adder.vhd" 27 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "or2a or2a:u3 " "Info: Elaborating entity \"or2a\" for hierarchy \"or2a:u3\"" {  } { { "f_adder.vhd" "u3" { Text "D:/Quatus2/works/summrize/f_adder/f_adder.vhd" 29 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "7 " "Info: Implemented 7 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "2 " "Info: Implemented 2 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 02 19:25:50 2008 " "Info: Processing ended: Sun Nov 02 19:25:50 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}