or2a.vhd

全加器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY or2a IS
	PORT
	(
		a,b		: IN	STD_LOGIC;
		c   	: OUT	STD_LOGIC
	);
END or2a;
ARCHITECTURE a OF or2a IS
BEGIN
	c<=a OR b;
END a;