📄 f_adder.fit.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--C1L1 is or2a:u3|c~42 at LC_X1_Y1_N4
--operation mode is normal
C1L1 = bin & (cin # ain) # !bin & cin & ain;
--B2L1 is h_adder:u2|so~15 at LC_X1_Y1_N2
--operation mode is normal
B2L1 = bin # cin # ain;
--bin is bin at PIN_61
--operation mode is input
bin = INPUT();
--cin is cin at PIN_62
--operation mode is input
cin = INPUT();
--ain is ain at PIN_58
--operation mode is input
ain = INPUT();
--cout is cout at PIN_60
--operation mode is output
cout = OUTPUT(C1L1);
--sum is sum at PIN_59
--operation mode is output
sum = OUTPUT(B2L1);
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