dds.txt

输出波形频率调整问题； 波形精度问题； 滤波问题； 多种指标输出（电压、电流、功率、相位）； 自身优点（任意波形发生器）。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY  DAC  IS
PORT ( 
	CLK : 	IN 	STD_LOGIC;
	DD : 	OUT   INTEGER RANGE 255 DOWNTO 0  );
END;
ARCHITECTURE a OF DAC IS
   SIGNAL Q    : INTEGER RANGE 63 DOWNTO 0 ;
   SIGNAL D   : INTEGER RANGE 255 DOWNTO 0 ;   --正弦信号输出
BEGIN
	PROCESS(CLK)
	BEGIN
		IF (CLK'EVENT AND CLK = '1') THEN  Q <= Q + 1;
   		END IF;
	END PROCESS;
PROCESS(Q)
BEGIN
 CASE Q IS        
WHEN 00=> D<=255; WHEN 01=> D<=254; WHEN 02=> D<=252; WHEN 03=> D<=249;
WHEN 04=> D<=245; WHEN 05=> D<=239; WHEN 06=> D<=233; WHEN 07=> D<=225;
WHEN 08=> D<=217; WHEN 09=> D<=207; WHEN 10=> D<=197; WHEN 11=> D<=186;
WHEN 12=> D<=174; WHEN 13=> D<=162; WHEN 14=> D<=150; WHEN 15=> D<=137;
WHEN 16=> D<=124; WHEN 17=> D<=112; WHEN 18=> D<= 99; WHEN 19=> D<= 87;
WHEN 20=> D<= 75; WHEN 21=> D<= 64; WHEN 22=> D<= 53; WHEN 23=> D<= 43;
WHEN 24=> D<= 34; WHEN 25=> D<= 26; WHEN 26=> D<= 19; WHEN 27=> D<= 13;
WHEN 28=> D<=  8; WHEN 29=> D<=  4; WHEN 30=> D<=  1; WHEN 31=> D<=  0;
WHEN 32=> D<=  0; WHEN 33=> D<=  1; WHEN 34=> D<=  4; WHEN 35=> D<=  8;
WHEN 36=> D<= 13; WHEN 37=> D<= 19; WHEN 38=> D<= 26; WHEN 39=> D<= 34;
WHEN 40=> D<= 43; WHEN 41=> D<= 53; WHEN 42=> D<= 64; WHEN 43=> D<= 75;
WHEN 44=> D<= 87; WHEN 45=> D<= 99; WHEN 46=> D<=112; WHEN 47=> D<=124;
WHEN 48=> D<=137; WHEN 49=> D<=150; WHEN 50=> D<=162; WHEN 51=> D<=174;
WHEN 52=> D<=186; WHEN 53=> D<=197; WHEN 54=> D<=207; WHEN 55=> D<=217;
WHEN 56=> D<=225; WHEN 57=> D<=233; WHEN 58=> D<=239; WHEN 59=> D<=245;
WHEN 60=> D<=249; WHEN 61=> D<=252; WHEN 62=> D<=254; WHEN 63=> D<=255;
WHEN OTHERS => NULL ;
END CASE;
END PROCESS;
DD <= D；
END;