ram.sim.rpt

nios 中读写sdram的程序

; Total output ports with no 1/0-value coverage       ; 3            ;
; Total output ports with no 1-value coverage         ; 4            ;
; Total output ports with no 0-value coverage         ; 6            ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                        ;
+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                         ; Output Port Name                                                                            ; Output Port Type ;
+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------+
; |ram|lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0 ; |ram|lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[0] ; portbdataout0    ;
; |ram|lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0 ; |ram|lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[1] ; portbdataout1    ;
; |ram|lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0 ; |ram|lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[2] ; portbdataout2    ;
; |ram|lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0 ; |ram|lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[3] ; portbdataout3    ;
; |ram|lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0 ; |ram|lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[4] ; portbdataout4    ;
; |ram|lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0 ; |ram|lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[5] ; portbdataout5    ;
; |ram|lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0 ; |ram|lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[6] ; portbdataout6    ;
; |ram|lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|ram_block1a0 ; |ram|lpm_ram_dp0:inst|altsyncram:altsyncram_component|altsyncram_47r1:auto_generated|q_b[7] ; portbdataout7    ;
; |ram|q[7]                                                                                         ; |ram|q[7]                                                                                   ; padio            ;
; |ram|q[6]                                                                                         ; |ram|q[6]                                                                                   ; padio            ;
; |ram|q[5]                                                                                         ; |ram|q[5]                                                                                   ; padio            ;
; |ram|q[4]                                                                                         ; |ram|q[4]                                                                                   ; padio            ;
; |ram|q[3]                                                                                         ; |ram|q[3]                                                                                   ; padio            ;
; |ram|q[2]                                                                                         ; |ram|q[2]                                                                                   ; padio            ;
; |ram|q[1]                                                                                         ; |ram|q[1]                                                                                   ; padio            ;
; |ram|q[0]                                                                                         ; |ram|q[0]                                                                                   ; padio            ;
; |ram|clock                                                                                        ; |ram|clock~corein                                                                           ; combout          ;
; |ram|data[7]                                                                                      ; |ram|data[7]~corein                                                                         ; combout          ;
; |ram|wraddress[0]                                                                                 ; |ram|wraddress[0]~corein                                                                    ; combout          ;
; |ram|wraddress[1]                                                                                 ; |ram|wraddress[1]~corein                                                                    ; combout          ;
; |ram|wraddress[2]                                                                                 ; |ram|wraddress[2]~corein                                                                    ; combout          ;
; |ram|wraddress[3]                                                                                 ; |ram|wraddress[3]~corein                                                                    ; combout          ;
; |ram|wraddress[4]                                                                                 ; |ram|wraddress[4]~corein                                                                    ; combout          ;
; |ram|wraddress[5]                                                                                 ; |ram|wraddress[5]~corein                                                                    ; combout          ;
; |ram|rdaddress[0]                                                                                 ; |ram|rdaddress[0]~corein                                                                    ; combout          ;
; |ram|rdaddress[1]                                                                                 ; |ram|rdaddress[1]~corein                                                                    ; combout          ;
; |ram|rdaddress[2]                                                                                 ; |ram|rdaddress[2]~corein                                                                    ; combout          ;
; |ram|rdaddress[3]                                                                                 ; |ram|rdaddress[3]~corein                                                                    ; combout          ;
; |ram|rdaddress[4]                                                                                 ; |ram|rdaddress[4]~corein                                                                    ; combout          ;
; |ram|data[6]                                                                                      ; |ram|data[6]~corein                                                                         ; combout          ;
; |ram|data[5]                                                                                      ; |ram|data[5]~corein                                                                         ; combout          ;
; |ram|data[4]                                                                                      ; |ram|data[4]~corein                                                                         ; combout          ;
; |ram|data[3]                                                                                      ; |ram|data[3]~corein                                                                         ; combout          ;
; |ram|data[2]                                                                                      ; |ram|data[2]~corein                                                                         ; combout          ;
; |ram|data[1]                                                                                      ; |ram|data[1]~corein                                                                         ; combout          ;
; |ram|data[0]                                                                                      ; |ram|data[0]~corein                                                                         ; combout          ;
; |ram|clock~clkctrl                                                                                ; |ram|clock~clkctrl                                                                          ; outclk           ;
+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+-----------------------------------------------------------------+
; Missing 1-Value Coverage                                        ;
+-------------------+--------------------------+------------------+
; Node Name         ; Output Port Name         ; Output Port Type ;
+-------------------+--------------------------+------------------+
; |ram|wren         ; |ram|wren~corein         ; combout          ;
; |ram|wraddress[7] ; |ram|wraddress[7]~corein ; combout          ;
; |ram|rdaddress[6] ; |ram|rdaddress[6]~corein ; combout          ;
; |ram|rdaddress[7] ; |ram|rdaddress[7]~corein ; combout          ;
+-------------------+--------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+-----------------------------------------------------------------+
; Missing 0-Value Coverage                                        ;
+-------------------+--------------------------+------------------+
; Node Name         ; Output Port Name         ; Output Port Type ;
+-------------------+--------------------------+------------------+
; |ram|rden         ; |ram|rden~corein         ; combout          ;
; |ram|wraddress[6] ; |ram|wraddress[6]~corein ; combout          ;
; |ram|wraddress[7] ; |ram|wraddress[7]~corein ; combout          ;
; |ram|rdaddress[5] ; |ram|rdaddress[5]~corein ; combout          ;
; |ram|rdaddress[6] ; |ram|rdaddress[6]~corein ; combout          ;
; |ram|rdaddress[7] ; |ram|rdaddress[7]~corein ; combout          ;
+-------------------+--------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Sat Aug 23 14:02:49 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off ram -c ram
Info: Using vector source file "E:/ram/ram.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      84.09 %
Info: Number of transitions in simulation is 1486
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 103 megabytes of memory during processing
    Info: Processing ended: Sat Aug 23 14:02:50 2008
    Info: Elapsed time: 00:00:01